Principal RTL Design Engineer

microTECH Global Limited; France; Hybride; EUR 70 000 - 100 000; Plein temps

Avantages offerts par ce poste

Hybrid work model

Résumé du poste

microTECH Global Limited in Aix-en-Provence, France, seeks a Principal RTL Design Engineer to drive the IP design for PCIe/CXL/AMBA blocks and implement them in SystemVerilog.

You will collaborate with verification and prototype IPs on leading-edge FPGAs, ensuring RTL quality and international teamwork.

Qualifications

• Knowledge of PCIe and CXL interfaces.
• RTL coding using Verilog/SystemVerilog.
• Strong English communication and collaboration skills.
• Minimum 5+ years of RTL design experience.

Responsabilités

• Contribute to architecture and micro-architecture of PCIe/CXL/AMBA IP.
• Implement designs in SystemVerilog.
• Collaborate with verification team to verify IPs.
• Prototype IPs on cutting-edge FPGAs.

Connaissances

PCIe/CXL knowledge

RTL coding SystemVerilog

English communication

Formation

Master's or PhD in EE/CE

Description du poste

Job Title: Principal RTL Design Engineer

Location: France, Aix en Provence

Job Type: Permanent

Salary: Dependant on experience

Role Overview:

Seeking a full time Senior Design Engineer to join the IP Design Team.

Key Responsibilities:

• Contribute to the architecture and micro-architecture of next generation PCIe / CXL / AMBA controller IP
• Implement these designs in System Verilog
• Collaborate with the verification team to verify the IPs
• Participate in prototyping of the IPs in cutting edge FPGAs

Experience Required:

• Knowledge of PCIe / CXL
• RTL coding: Verilog / System Verilog
• Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent.
• Minimum of 5+ years of experience with RTL Design
• Good English skills, communication skills, and willingness to work with an international team.

What’s Offered:

Hybrid remote with 2-3 days/week onsite in Aix-en-Provence.

Not considering overseas relocation, or complex Visa candidates currently.