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Semiengineering is seeking a Principal Verification Engineer to lead the development of advanced test benches for next-generation interconnect IP architectures and to enable verification of configurable chiplet designs.
You will be part of the Advanced Engineering team and help shape the future of System-on-Chip design.
This role focuses on coordinating activities, defining RTL verification tests, and achieving robust coverage at the system level.
As a Principal Verification Engineer, you will play a leading role in developing the next generation of Arteris IP solutions, enabling verification of highly configurable chiplet interconnect architectures.
You will be part of the Advanced Engineering team and help shape the future of System-on-Chip design.