Senior PCIe/CXL RTL Design Architect (Hybrid)

Rambus; Aix-en-Provence; Hybrid; EUR 70,000 - 110,000; Full time

Benefits offered by this job

Health insurance

Employee Stock Purchase Plan

Extra vacation day per quarter

Team lunches and breakfasts

Great team atmosphere

Job summary

Rambus is seeking a Senior Design engineer in Aix-en-Provence to contribute to architecture and micro-architecture of PCIe/CXL/IP. The role involves SystemVerilog implementation and collaboration with verification teams, including prototyping IPs on FPGAs.

You will join a hybrid setup with onsite and remote work, joining a multicultural team. A Master’s or PhD in EE/CE and 5+ years RTL design experience are expected, with strong English communication skills.

Qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or equivalent.
• 5+ years of experience with RTL Design
• Good English skills and willingness to work with an international team.
• Knowledge of PCIe / CXL

Responsibilities

• Contribute to the architecture and micro-architecture of next generation PCIe / CXL / AMBA controller IP
• Implement these designs in System Verilog
• Collaborate with the verification team to verify the IPs
• Participate in prototyping of the IPs in cutting edge FPGAs

Skills

RTL Design

English proficiency

PCIe knowledge

SystemVerilog

Education

Master's or PhD in Electrical or Computer Engineering

Tools

SystemVerilog

FPGA prototyping

Job description

Rambus is seeking a Senior Design engineer in Aix-en-Provence to contribute to architecture and micro-architecture of PCIe/CXL/IP. The role involves SystemVerilog implementation and collaboration with verification teams, including prototyping IPs on FPGAs.

You will join a hybrid setup with onsite and remote work, joining a multicultural team. A Master’s or PhD in EE/CE and 5+ years RTL design experience are expected, with strong English communication skills.