Verification Lead – 4-Core Coherent AI System (Barcelona)

Semidynamics; Barcelona; Hybrid; EUR 120,000 - 180,000; Full time

Benefits offered by this job

4 days per week in Barcelona office

Work from home 1 day

Competitive package

Job summary

Semidynamics in Barcelona is seeking a senior verification leader to own the verification strategy for a memory-centric AI system. You will lead a small team of verification leads, shape the verification plan, and drive through tape-out sign-off with cross-functional partners.

Requires 12+ years in design verification, strong SystemVerilog/UVM expertise, and proven leadership in complex SoC projects. Domestic and international emulation/CI experience a plus. Fluent English mandatory.

Qualifications

• 12+ years of hands-on design verification.
• Architected reusable, multi-agent environments using SystemVerilog/UVM.
• Defined a verification plan, drove coverage closure and guided other engineers.
• Hands-on experience verifying cache-coherent multi-core systems or subsystems.
• Experience with a major simulator and debugger (Questa, VCS or Xcelium).
• Working knowledge of SoC bus protocols: AXI, CHI.
• Formal verification experience is a plus.
• Scripting (Python, Bash) and CI infrastructure (GitLab).
• Emulation and post-silicon debug capabilities.

Responsibilities

• Own the verification strategy for a 4-core coherent system.
• Write the verification plan: what is checked where, by whom, and how we know we are done.
• Set and track sign-off criteria for tape-out: functional and code coverage, bug trends, open risks.
• Decide where simulation, emulation and FPGA give best return with team leads.
• Lead the team of 3-4 verification leads.
• Hire and grow the team: recruit engineers, mentor the leads, set clear goals.
• Ensure healthy regressions and CI, push automation.
• Be the verification voice in arch reviews and report status to PM.
• Run the project and plan/estimate verification effort.
• Track tape-out risks and mitigations.
• Manage EDA licences and compute resources.

Skills

SystemVerilog

UVM

Technical leadership

Python

Bash

CI infrastructure

Formal verification

Emulation

Post-silicon debug

Integration verification

Fluent English

Education

B.Sc. or M.Sc. in Electrical or Computer Engineering

Tools

Questa

VCS

Xcelium

Visualizer

Verdi

Palladium

ZeBu

Veloce

Job description

Semidynamics in Barcelona is seeking a senior verification leader to own the verification strategy for a memory-centric AI system. You will lead a small team of verification leads, shape the verification plan, and drive through tape-out sign-off with cross-functional partners.

Requires 12+ years in design verification, strong SystemVerilog/UVM expertise, and proven leadership in complex SoC projects. Domestic and international emulation/CI experience a plus. Fluent English mandatory.