Senior LSU Verifier - Hybrid, Barcelona (4d onsite)

Semidynamics; Barcelona; Hybrid; EUR 70,000 - 100,000; Full time

Benefits offered by this job

4 days per week in Barcelona office (1

1 WFH day per week

Work from anywhere for 1 week

Competitive package

Job summary

Semidynamics is seeking an experienced LSU verification engineer to own the verification plan for a Load/Store Unit in a CPU/GPU core. You will drive RTL freeze to tapeout‑quality sign‑off and mentor junior engineers while collaborating with DV leads.

You will build UVM testbenches, develop constrained tests for memory ordering and forwarding, and push formal verification to strengthen coverage. Barcelona hybrid role with global collaboration.

Qualifications

• BS/MS in EE/CE/CS, 5+ years in ASIC functional verification.
• Strong SystemVerilog/UVM experience; hands‑on testbench architecture.
• Deep understanding of memory subsystems: cache hierarchies, TLBs, memory consistency models, load/store pipelines.
• Knowledge of RISC‑V ISA and privileged specification is mandatory.
• Knowledge of AMBA AXI4, AXI5Lite and CHI is mandatory.
• Experience with coverage‑driven verification and regression management.
• Debugging complex RTL failures using waveform tools (Verdi/DVE or similar).

Responsibilities

• Define and own the LSU verification plan with coverage and closure criteria.
• Build/extend UVM components: drivers, monitors, scoreboards, models.
• Develop directed and constrained tests for forwarding, ordering, and faults.
• Drive formal verification for ordering/coherence where needed.
• Debug RTL/testbench failures with design teams; root-cause analysis.
• Track and close functional/code coverage; report status to leads.
• Mentor junior verification engineers; review testbench code and plans.
• Interface with architecture/design/DV leads to resolve issues.

Skills

SystemVerilog/UVM

Memory subsystems

RISC‑V ISA knowledge

AMBA AXI4/AXI5Lite/CHI

Coverage-driven verification

RTL debugging with waveform tools

Testbench architecture

Education

BS/MS in EE/CE/CS

Tools

Verdi/DVE

JasperGold

Job description

Semidynamics is seeking an experienced LSU verification engineer to own the verification plan for a Load/Store Unit in a CPU/GPU core. You will drive RTL freeze to tapeout‑quality sign‑off and mentor junior engineers while collaborating with DV leads.

You will build UVM testbenches, develop constrained tests for memory ordering and forwarding, and push formal verification to strengthen coverage. Barcelona hybrid role with global collaboration.