Senior Verification Engineer - Memory Subsystem & Cache

Hireroo Ltd; Barcelona; Híbrido; EUR 75.000 - 105.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Flexible working hours

Hybrid model

Relocation support

Private medical insurance

Language classes

Descripción de la vacante

Hireroo Ltd. in Barcelona, Spain, seeks a Senior Verification Engineer to own LSU verification of a processor core, memory ordering, cache, TLB interactions, and related bus interfaces.

You will lead planning through sign-off, collaborating with architecture, RTL and other verification teams. The role is hybrid in Barcelona, with senior-level responsibilities including testbench development, coverage closure, defect analysis and mentoring of juniors.

Formación

• 5+ years of ASIC functional verification experience.
• Strong SystemVerilog and UVM experience.
• Hands-on testbench architecture experience.
• Deep understanding of LSU, caches, TLBs and memory subsystems.
• Strong knowledge of memory consistency and load/store pipelines.
• RISC V ISA and privileged specification familiarity.
• Experience with AXI4/AXI5 Lite and CHI.
• Coverage driven verification and regression management.

Responsabilidades

• Own the LSU verification plan, test strategy and closure criteria.
• Build and extend UVM testbench components (drivers, monitors, scoreboards).
• Develop directed and constrained random tests.
• Verify store-to-load forwarding and memory ordering.
• Verify speculative loads and vector memory accesses.
• Cover misaligned and split accesses, exceptions and faults.
• Verify cache, TLB and load/store pipeline interactions.
• Drive functional and code coverage closure; manage regressions.
• Apply formal verification to ordering or coherency properties as needed.
• Debug RTL and testbench failures and perform root-cause analysis.
• Resolve cross-unit verification issues with architecture/design teams.
• Review verification code and mentor junior engineers.

Conocimientos

ASIC verification

SystemVerilog

UVM

Testbench architecture

RISC-V ISA

Memory subsystems

Memory ordering

RTL debugging

Verdi/DVE

Educación

BS/MS in Electrical Engineering/Computer Engineering/CS

Herramientas

Verdi

DVE

Descripción del empleo

Hireroo Ltd. in Barcelona, Spain, seeks a Senior Verification Engineer to own LSU verification of a processor core, memory ordering, cache, TLB interactions, and related bus interfaces.

You will lead planning through sign-off, collaborating with architecture, RTL and other verification teams. The role is hybrid in Barcelona, with senior-level responsibilities including testbench development, coverage closure, defect analysis and mentoring of juniors.