Senior Verification - LSU (Load/Store Unit) and Data Cache

Semidynamics; Barcelona; Hybrid; EUR 70,000 - 100,000; Full time

Benefits offered by this job

4 days per week in Barcelona office (1

1 WFH day per week

Work from anywhere for 1 week

Competitive package

Job summary

Semidynamics is seeking an experienced LSU verification engineer to own the verification plan for a Load/Store Unit in a CPU/GPU core. You will drive RTL freeze to tapeout‑quality sign‑off and mentor junior engineers while collaborating with DV leads.

You will build UVM testbenches, develop constrained tests for memory ordering and forwarding, and push formal verification to strengthen coverage. Barcelona hybrid role with global collaboration.

Qualifications

• BS/MS in EE/CE/CS, 5+ years in ASIC functional verification.
• Strong SystemVerilog/UVM experience; hands‑on testbench architecture.
• Deep understanding of memory subsystems: cache hierarchies, TLBs, memory consistency models, load/store pipelines.
• Knowledge of RISC‑V ISA and privileged specification is mandatory.
• Knowledge of AMBA AXI4, AXI5Lite and CHI is mandatory.
• Experience with coverage‑driven verification and regression management.
• Debugging complex RTL failures using waveform tools (Verdi/DVE or similar).

Responsibilities

• Define and own the LSU verification plan with coverage and closure criteria.
• Build/extend UVM components: drivers, monitors, scoreboards, models.
• Develop directed and constrained tests for forwarding, ordering, and faults.
• Drive formal verification for ordering/coherence where needed.
• Debug RTL/testbench failures with design teams; root-cause analysis.
• Track and close functional/code coverage; report status to leads.
• Mentor junior verification engineers; review testbench code and plans.
• Interface with architecture/design/DV leads to resolve issues.

Skills

SystemVerilog/UVM

Memory subsystems

RISC‑V ISA knowledge

AMBA AXI4/AXI5Lite/CHI

Coverage-driven verification

RTL debugging with waveform tools

Testbench architecture

Education

BS/MS in EE/CE/CS

Tools

Verdi/DVE

JasperGold

Job description

Role summary

Own verification of the Load/Store Unit, data cache and bus interfaces for a CPU/GPU core — the block handling memory ordering, address generation, cache/TLB interaction, forwarding, and exception handling. Contribute to drive the LSU from RTL freeze to tapeout-quality sign-off.

Responsibilities

• Define and own the LSU verification plan: functional coverage, testplan, checkers, and closure criteria
• Build/extend UVM testbench components for LSU (drivers, monitors, scoreboards, memory models)
• Develop directed and constrained-random tests covering store-to-load forwarding, memory ordering (RISC-V WMO model), speculative loads, vector accesses, misaligned/split accesses, exceptions/faults, and pipeline hazards
• Drive formal verification for ordering/coherence properties where simulation coverage is weak
• Debug RTL/testbench failures in collaboration with design; triage and root-cause
• Track and close functional/code coverage; report verification status to program leads
• Mentor junior verification engineers; review testbench code and testplans
• Interface with architecture, design, and DV leads on other units to resolve cross-unit issues.

Required qualifications

• BS/MS in EE/CE/CS, 5+ years in ASIC functional verification.
• Strong SystemVerilog/UVM experience; hands‑on testbench architecture
• Deep understanding of memory subsystems: cache hierarchies, TLBs, memory consistency models, load/store pipelines
• Knowledge of RISC‑V ISA and privileged specification is mandatory
• Knowledge of AMBA AXI4, AXI5Lite and CHI is mandatory
• Experience with coverage‑driven verification and regression management
• Debugging complex RTL failures using waveform tools (Verdi/DVE or similar)

Preferred

• Formal verification experience (JasperGold or similar) applied to memory ordering/coherence
• Knowledge of CPU architecture and memory execution pipeline
• Prior LSU, cache, or memory‑controller verification specifically
• Experience with RISC‑V, ARM, or x86 memory models
• Scripting (Python/Perl) for verification infrastructure and regression automation
• Prior team lead or mentorship experience

Nice to Have

• Emulation platforms (Veloce, ZeBu)
• Familiarity with fuzzing techniques (AFL++)
• Knowledge of SystemC/C++ testbenches

Essential Soft Skills

• An adversarial, gap‑seeking mindset — instinctively asks "who actually checks this?" — collaborative relationship with the whole core.
• Clear communication across DV, design, and software teams; writes verification plans others can follow.

Why Semidynamics?

• Work at one of Europe's most promising deep‑tech semiconductor scale-ups.
• Accelerated development path.
• 4 days per week in the Barcelona office (city center), 1 WFH day.
• 1 week of work from everywhere in the world.
• Competitive package.
• A collaborative, technical, and growth‑oriented environment that values direct ownership and clear thinking.