Senior Formal Verification Lead — Hybrid, AI-Driven SoC

Openchip & Software Technologies; Barcelona; Hybrid; EUR 90,000 - 120,000; Full time

Benefits offered by this job

Hybrid work model

Autonomy and ownership

European collaboration

Job summary

Openchip & Software Technologies S.L. is seeking a Senior Formal Verification Engineer to lead the formal verification strategy across our SoC platforms.

You will work with system architects to establish verification environments, write SystemVerilog assertions, and guide the use of formal methods to improve IP and chip-level verification efficiency. You will design verification methodologies, create multi-level test plans, analyze coverage, and participate in regression frameworks and project

Qualifications

• Master's degree in relevant field.
• Min 5 years of experience in Formal Verification.
• Deep understanding of formal verification concepts at SoC level.
• Significant contributions in formal verification.
• Experience with SystemVerilog and SV assertions.

Responsibilities

• Establish formal verification environment with system architects and design team.
• Guide use of formal verification to improve IP/SoC verification efficiency.
• Define Formal Verification Methodologies.
• Produce IP/subsystem/chip level test plans from design docs.
• Write and debug SystemVerilog assertions.
• Analyze coverage and address holes with design teams.
• Develop framework for regression runs and debugging failures.
• Support integration and test planning of designs at subsystem level.
• Iterate workflows with scripting/AI techniques to streamline processes.
• Participate in project reviews and provide guidance to teammates.

Skills

Formal verification

SystemVerilog

SV assertions

Scripting

Debugging

CPU/NoC/Memory

Education

Master's degree

Tools

Formal tools

SystemVerilog

Job description

Openchip & Software Technologies S.L. is seeking a Senior Formal Verification Engineer to lead the formal verification strategy across our SoC platforms.

You will work with system architects to establish verification environments, write SystemVerilog assertions, and guide the use of formal methods to improve IP and chip-level verification efficiency. You will design verification methodologies, create multi-level test plans, analyze coverage, and participate in regression frameworks and project