Design Verification Engineer: GLS & Emulation (4D/Barcelona)

Semidynamics; Barcelona; Hybrid; EUR 48,000 - 64,000; Full time

Benefits offered by this job

Hybrid work

Barcelona office

Competitive package

Global exposure

Job summary

Semidynamics in Barcelona is seeking a Design Verification Engineer to support gate-level simulation and hardware emulation for our AI chip design teams. You will validate post-synthesis netlists, debug timing and reset issues, and enable large-scale emulation of SoC designs prior to tapeout.

This hands-on role requires close collaboration with RTL design, DFT, physical design and firmware teams, plus bringing up emulation models for pre-silicon software validation and performance profiling.

Qualifications

• 3+ years in ASIC/SoC design verification with gate-level simulation.

Responsibilities

• Set up, run, and debug GLS for functional, timing, and low-power verification.
• Support hardware emulation platforms (Veloce, Palladium, ZeBu) including bring-up and regression management.
• Debug RTL vs gate-level mismatches, timing violations, and clock/reset domain issues.
• Develop and maintain testbenches, scripts, and flows for GLS and emulation cycles.
• Collaborate with DFT to validate scan, ATPG, and BIST in GLS/emulation environments.
• Work with physical design/STA to resolve SDF annotation and back-annotated discrepancies.
• Bring up emulation models for pre-silicon software validation and profiling.
• Triage and root-cause simulation/emulation failures and track issues cross-functionally.
• Optimize runtimes and capacity for large SoC designs; document methodologies and known issues.

Skills

ASIC/SoC verification

Verilog/SystemVerilog

SDF timing

Emulation

Debugging

Education

Bachelor's or Master’s in Electrical/Computer Engineering

Tools

VCS

Xcelium

Questa

Palladium/ZeBu/Veloce

Job description

Semidynamics in Barcelona is seeking a Design Verification Engineer to support gate-level simulation and hardware emulation for our AI chip design teams. You will validate post-synthesis netlists, debug timing and reset issues, and enable large-scale emulation of SoC designs prior to tapeout.

This hands-on role requires close collaboration with RTL design, DFT, physical design and firmware teams, plus bringing up emulation models for pre-silicon software validation and performance profiling.