Lead Design Verification Engineer

Beagle; Barcelona; On-site; EUR 140,000 - 190,000; Full time

Job summary

Beagle is seeking an experienced Lead Design Verification Engineer to own the verification of high‑speed interfaces in cutting‑edge AI SoC designs. You will architect SystemVerilog/UVM environments, drive coverage plans, and lead a team toward sign-off.

Required are 10+ years in ASIC/SoC verification, deep PCIe/UCIe and AMBA protocol knowledge, and hands‑on ability with SystemVerilog/UVM. Strong leadership and collaboration across RTL, firmware and architecture are essential.

Qualifications

• 10+ years ASIC/SoC design verification experience.
• Hands-on verification of high-speed interfaces.
• Strong knowledge of PCIe/UCIe and AMBA protocols.

Responsibilities

• Lead subsystem and IP-level verification for high-speed interfaces.
• Develop reusable SystemVerilog/UVM environments and testbenches.
• Define verification strategies, plans and sign-off criteria.
• Mentor verification engineers and drive timely delivery.
• Collaborate with RTL design, architecture and firmware teams.
• Optimize simulation, regression, and coverage analysis.

Skills

SystemVerilog

UVM

Testbench development

Coverage-driven verification

Sign-off experience

Leadership

Education

Electrical/Computer Engineering degree

Tools

Synopsys VCS

Cadence Xcelium

Siemens Questa

Job description

We are currently looking for an experienced Lead Design Verification Engineer to join an innovative semiconductor business developing advanced AI SoC and high-performance silicon technologies.

This is an exciting opportunity for a senior verification specialist to take technical ownership of complex subsystem and IP-level verification, focusing on high-speed interface protocols and next-generation SoC architectures.

Key Responsibilities

• Lead subsystem and IP-level functional verification of high-speed interfaces within complex AI SoC designs.
• Architect, develop and maintain reusable SystemVerilog/UVM-based verification environments, testbenches and components.
• Provide technical expertise across high-speed protocols, including PCIe, UCIe and SerDes, alongside AMBA protocols such as AXI, AHB, CHI and CXS.
• Define verification strategies, test plans, coverage models and sign-off criteria.
• Lead, mentor and support verification engineers, driving quality and delivery through to sign-off.
• Debug complex RTL and functional issues, perform root-cause analysis and collaborate with design and architecture teams.
• Optimise simulation, regression, automation and coverage-analysis flows.
• Work closely with RTL design, SoC architecture, firmware and cross-functional engineering teams to resolve integration challenges.

Experience Required

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or a related discipline.
• 10+ years of ASIC/SoC design verification experience, including recent hands-on high-speed interface verification.
• Strong expertise in PCIe, UCIe, SerDes or related high-speed communication protocols.
• In-depth knowledge of AMBA protocols, including AXI, AHB, CHI and CXS.
• Extensive experience with SystemVerilog, UVM, testbench development and coverage-driven verification.
• Proven track record of functional coverage closure and verification sign-off.
• Strong understanding of digital design principles, SoC architectures and subsystem integration.
• Experience with industry-standard simulation tools such as Synopsys VCS, Cadence Xcelium or Siemens Questa.
• Demonstrable technical leadership, mentoring and cross-functional collaboration skills.