Verification Architect for AI SoC & High-Speed Interfaces

Beagle; Barcelona; On-site; EUR 140,000 - 190,000; Full time

Job summary

Beagle is seeking an experienced Lead Design Verification Engineer to own the verification of high‑speed interfaces in cutting‑edge AI SoC designs. You will architect SystemVerilog/UVM environments, drive coverage plans, and lead a team toward sign-off.

Required are 10+ years in ASIC/SoC verification, deep PCIe/UCIe and AMBA protocol knowledge, and hands‑on ability with SystemVerilog/UVM. Strong leadership and collaboration across RTL, firmware and architecture are essential.

Qualifications

• 10+ years ASIC/SoC design verification experience.
• Hands-on verification of high-speed interfaces.
• Strong knowledge of PCIe/UCIe and AMBA protocols.

Responsibilities

• Lead subsystem and IP-level verification for high-speed interfaces.
• Develop reusable SystemVerilog/UVM environments and testbenches.
• Define verification strategies, plans and sign-off criteria.
• Mentor verification engineers and drive timely delivery.
• Collaborate with RTL design, architecture and firmware teams.
• Optimize simulation, regression, and coverage analysis.

Skills

SystemVerilog

UVM

Testbench development

Coverage-driven verification

Sign-off experience

Leadership

Education

Electrical/Computer Engineering degree

Tools

Synopsys VCS

Cadence Xcelium

Siemens Questa

Job description

Beagle is seeking an experienced Lead Design Verification Engineer to own the verification of high‑speed interfaces in cutting‑edge AI SoC designs. You will architect SystemVerilog/UVM environments, drive coverage plans, and lead a team toward sign-off.

Required are 10+ years in ASIC/SoC verification, deep PCIe/UCIe and AMBA protocol knowledge, and hands‑on ability with SystemVerilog/UVM. Strong leadership and collaboration across RTL, firmware and architecture are essential.