Design Verification Engineer – GLS & Hardware Emulation

Hireroo Ltd; Barcelona; Híbrido; EUR 65 000 - 95 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

Flexible working hours

Hybrid model

1 week per year working from anywhere

25 days annual leave plus December 24/

December 31

Monthly food allowance

Private medical insurance

Relocation bonus

Housing search support

Visa support

Family relocation support

Virtual shares

Language classes

Tax incentive

Resumo da oferta

Hireroo Ltd in Barcelona seeks a Design Verification Engineer to drive gate-level simulation, hardware emulation and timing verification for advanced ASIC/SoC designs. You will collaborate with RTL, DFT, physical design and firmware teams to validate synthesized designs before silicon.

Mid to senior level, you will optimize simulation performance, automate workflows, debug RTL/netlist mismatches, and support emulation bring-up on hardware platforms while contributing to power, timing and

Qualificações

• 3+ years of ASIC or SoC verification experience
• Degree in Electrical or Computer Engineering or related field
• Practical gate level simulation experience
• Hardware emulation or FPGA prototyping experience
• Verilog/SystemVerilog
• VCS, Xcelium or Questa
• SDF annotation and timing simulation
• Clocking, reset and STA fundamentals
• Low power concepts, UPF/CPF
• Python, Perl or TCL scripting
• Git/Perforce and LSF/Grid
• Strong debugging and problem solving skills

Responsabilidades

• Configure and debug gate level simulations (GLS)
• Perform functional, timing and power verification
• Support hardware emulation and system bring-up
• Debug RTL and netlist mismatches
• Investigate timing, reset and X propagation issues
• Implement SDF timing annotation
• Automate simulation and emulation workflows
• Support scan, ATPG and BIST verification
• Enable firmware testing through emulation
• Improve simulation performance and regression efficiency
• Collaborate with RTL, DFT and physical design teams

Conhecimentos

ASIC/SoC verification

Verilog/SystemVerilog

Scripting (Python/TCL/Perl)

Debugging and problem solving

Gate level simulation

Timing closure knowledge

Formação académica

Degree in Electrical or Computer Engineering

Ferramentas

VCS

Xcelium

Questa

Descrição da oferta de emprego

Hireroo Ltd in Barcelona seeks a Design Verification Engineer to drive gate-level simulation, hardware emulation and timing verification for advanced ASIC/SoC designs. You will collaborate with RTL, DFT, physical design and firmware teams to validate synthesized designs before silicon.

Mid to senior level, you will optimize simulation performance, automate workflows, debug RTL/netlist mismatches, and support emulation bring-up on hardware platforms while contributing to power, timing and