Lead Formal Verification - 4-Day Week, Barcelona Office

Semidynamics; Barcelona; On-site; EUR 70,000 - 90,000; Full time

Benefits offered by this job

Four-day week

Barcelona on-site

WFH day per week

Work from anywhere

Job summary

Semidynamics in Barcelona, Spain seeks a static formal verification lead to ensure functional correctness and low-power intent across the design lifecycle. You will drive RTL-to-Gate and Gate-to-Gate equivalence checks, debug LEC issues, and ensure seamless convergence between RTL, synthesis, and physical design for hierarchical designs.

The role requires 7+ years in Formal Verification/LEC, expertise with Synopsys Formality/VC LP, and strong scripting skills (TCL/Python/Perl).

Qualifications

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering or related discipline.
• 7+ years of experience in Formal Verification/LEC.
• Strong expertise in tools like Synopsys Formality/VC LP.
• Understanding of low-power design concepts (UPF).
• Experience with synthesis, netlist optimizations, and equivalence debugging.
• Proficiency in TCL, Python, or Perl.
• Experience with hierarchical Sub system level LEC flows.

Responsibilities

• Perform RTL-to-Gate and Gate-to-Gate equivalence checks using tools like Synopsys Formality
• Debug LEC failures, including issues arising from clock gating, retention, isolation, and level shifters
• Ensure convergence of LEC across synthesis, place-and-route, and ECO cycles
• Work closely with RTL, Synthesis, DFT, and Physical Design teams to resolve design mismatches
• Handle ECO validation and ensure equivalence closure post-design changes
• Develop automation scripts and improve methodology for LEC sign-off

Skills

Formal verification/LEC

Synopsys Formality

VC LP

UPF low-power concepts

RTL-to-Gate debugging

Scripting (TCL/Python/Perl)

Hierarchical LEC flows

Education

Bachelor’s or Master’s in Electrical/Electronics Engineering

Tools

Synopsys Formality

VC LP

Job description

Semidynamics in Barcelona, Spain seeks a static formal verification lead to ensure functional correctness and low-power intent across the design lifecycle. You will drive RTL-to-Gate and Gate-to-Gate equivalence checks, debug LEC issues, and ensure seamless convergence between RTL, synthesis, and physical design for hierarchical designs.

The role requires 7+ years in Formal Verification/LEC, expertise with Synopsys Formality/VC LP, and strong scripting skills (TCL/Python/Perl).