Lead SoC Physical Verification & Signoff Engineer

Aion Silicon Ltd; Barcelona; On-site; EUR 90,000 - 130,000; Full time

Job summary

Aion Silicon Ltd in Barcelona seeks an experienced SoC Physical Verification Engineer to drive signoff for next-generation logic, memory-centric SoCs, and advanced-node designs. You will ensure tapeout-ready silicon through comprehensive DRC, LVS, ERC, PERC, DFM, and reliability signoffs, collaborating with PD, CAD, RTL, and EDA vendors.

You will lead methodology, execution, and signoff while coordinating with Architecture, BUMP, and RDL routing teams, and interaction with foundries including

Qualifications

• Experience leading full-chip or block-level physical verification for advanced-node SoCs.
• Strong expertise in DRC, LVS, ERC, PERC, DFM, and reliability verification methods.
• Familiar with 22nm/16nm/7nm/5nm and below process nodes.
• Proven ability to develop automation and AI-assisted verification workflows.

Responsibilities

• Own and drive full-chip and hierarchical physical verification signoff, including DRC, LVS, ERC, PERC, Antenna, DFM, Density, Metal Fill, CMP and Reliability checks.
• Debug, customize, and deploy foundry-qualified rule decks, manage waivers, and ensure clean signoff closure for advanced-node designs.
• Perform reliability verification including ESD, latch-up, electromigration, floating nets, multi-power domain, and connectivity checks.
• Support parasitic RC extraction and correlation of verification results with implementation and silicon measurements.
• Develop and maintain physical verification automation, regression infrastructure, scripting frameworks, and AI-assisted workflows.
• Work closely with PD, CAD, RTL, Product Engineering, EDA vendors, and foundries (including direct TSMC interaction) from project kick-off through tapeout.

Skills

Physical verification leadership

Debugging & analysis

Scripting (Python/Tcl/Perl)

Cross-functional collaboration

AI-assisted verification workflows

Education

MS/PhD in Electrical Engineering or related field

Tools

Mentor Calibre

Synopsys IC Validator

Cadence Innovus

StarRC

Quantus

Job description

Aion Silicon Ltd in Barcelona seeks an experienced SoC Physical Verification Engineer to drive signoff for next-generation logic, memory-centric SoCs, and advanced-node designs. You will ensure tapeout-ready silicon through comprehensive DRC, LVS, ERC, PERC, DFM, and reliability signoffs, collaborating with PD, CAD, RTL, and EDA vendors.

You will lead methodology, execution, and signoff while coordinating with Architecture, BUMP, and RDL routing teams, and interaction with foundries including