Senior Verification Engineer – Next-Gen RISC-V CPUs (UVM)

Akuaro; Barcelona; On-site; EUR 70,000 - 100,000; Full time

Benefits offered by this job

Flexible working hours

Competitive compensation

Learning-driven culture

Visa sponsorship

Free Spanish lessons

Job summary

A European tech company in Barcelona is seeking a Senior Verification Engineer to ensure their next generation of silicon meets quality standards. You will develop UVM-based testbenches, define verification plans, and automate workflows. The ideal candidate has 8+ years of experience in digital design verification, strong scripting skills, and English fluency. This is a permanent position offering competitive compensation and flexible working hours.

Qualifications

• 8+ years of experience in digital design verification.
• Proven expertise in SystemVerilog and UVM for complex ASIC/SoC verification.
• English fluency (C1 or higher).

Responsibilities

• Develop and maintain UVM-based testbenches for digital designs.
• Define and implement comprehensive verification plans.
• Automate workflows with scripting for regression management.

Skills

SystemVerilog

UVM

Scripting (Python/Perl/Bash/TCL)

Digital design verification

Waveform debugging

Collaboration skills

Education

Master’s or PhD in Electronic Engineering or Computer Engineering

Tools

ModelSim

VCS

Xcelium

Git

SVN

Job description

A European tech company in Barcelona is seeking a Senior Verification Engineer to ensure their next generation of silicon meets quality standards. You will develop UVM-based testbenches, define verification plans, and automate workflows. The ideal candidate has 8+ years of experience in digital design verification, strong scripting skills, and English fluency. This is a permanent position offering competitive compensation and flexible working hours.