Senior DFT Engineer - Hybrid, Growth & Global Projects

Capgemini; Gaià; Hybrid; EUR 60,000 - 80,000; Full time

Benefits offered by this job

Hybrid work

Training and certifications

Health and life insurance

Referral program with bonuses

International projects

Job summary

Capgemini Engineering is seeking a Senior DFT Engineer to implement and verify advanced DFT solutions across complex SOCs. You will drive block- and top-level insertion, ATPG validation, and timing-aware testability while collaborating with Physical Design and STA teams.

You will develop robust test patterns, optimize fault coverage and support silicon bring-up, contributing to continuous improvements in DFT methodologies and automation.

Qualifications

• 6+ years hands-on experience with DFT and test flows for large SOCs.
• Knowledge of JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500, MBIST/LBIST.
• Experience with main EDA providers: Synopsys DFT Compiler, Tetramax, VCS, Tessent and Modus/Encounter tool suite.
• Proficiency in RTL simulation, synthesis, Linting, CDC and RDC checks, STA, DFT and quality metrics.
• Hands-on scripting in Perl/Tcl/Python.

Responsibilities

• Implement and verify DFT solutions across complex digital designs to ensure high test coverage.
• Perform block- and top-level DFT insertion and pattern validation.
• Develop, validate, and optimize ATPG patterns for test efficiency and fault coverage.
• Collaborate with Physical Design and STA teams to address timing constraints.
• Support silicon bring-up, failure analysis, and issue diagnosis across designs.
• Contribute to reviews and continuous improvement of DFT flows and automation.

Skills

DFT techniques

JTAG

ATPG

MBIST LBIST

RTL simulation

Synthesis

Python scripting

Education

Bachelors/Masters in EE/CE

Tools

Synopsys DFT Compiler

Tetramax

VCS

Tessent

Modus/Encounter

Job description

Capgemini Engineering is seeking a Senior DFT Engineer to implement and verify advanced DFT solutions across complex SOCs. You will drive block- and top-level insertion, ATPG validation, and timing-aware testability while collaborating with Physical Design and STA teams.

You will develop robust test patterns, optimize fault coverage and support silicon bring-up, contributing to continuous improvements in DFT methodologies and automation.