Senior DFT Architect for Mixed-Signal ASICs

Monolithic Power Spain S.L.; Barcelona; Presencial; EUR 90.000 - 120.000; Jornada completa

Descripción de la vacante

Monolithic Power Systems, Inc. in Barcelona, Spain, is seeking a Sr. DFT Engineer to lead end-to-end design, implementation, verification and debugging of Digital and Mixed-Signal ICs DFT architectures.

You will work on ATPG, SCAN, JTAG and other techniques, collaborate with Analog, Digital and Testing teams, and contribute to silicon bring-up and failure analysis. Strong Verilog/SystemVerilog skills and ASIC tool experience are required.

Formación

• Bachelor's or master's degree in electrical engineering or related field.
• 15+ years as a DFT engineer for ASICs or similar roles.
• Independent work style with strong collaboration across teams.
• Solid knowledge of full ASIC development process.
• Excellent RTL Verilog/SystemVerilog coding skills.

Responsabilidades

• Develop and implement DFT architectures and techniques.
• RTL design, debugging and verification of DFT-enabled blocks.
• Physical implementation, gate-level verification and testing.
• Create high-quality test and debug patterns.
• Perform STA and power analysis of DFT modes.
• Support silicon bring-up and failure analysis.
• Define DFT constraints for synthesis and P&R.
• Coordinate with Analog, Testing, Product and Digital teams.
• AMS verification for analog, digital and mixed-signal.

Conocimientos

RTL Verilog/SystemVerilog

DFT Architectures

ATPG/SCANT/IDDQ

Gate-Level Verification

JTAG/LBIST/MBIST

ATE implementation & failure backtr...

Synthesis/PEX/STA/Power

Verilog/SystemVerilog/UVM

CADENCE/Synopsys tools

Modus/Tetramax/TestInsight

Educación

Bachelor of Science in Electrical Engineering

Master of Science in Electrical Engineering

Herramientas

Cadence

Synopsys

Modus

Tetramax

Testsent

TestKompress

TestInsight

Descripción del empleo

Monolithic Power Systems, Inc. in Barcelona, Spain, is seeking a Sr. DFT Engineer to lead end-to-end design, implementation, verification and debugging of Digital and Mixed-Signal ICs DFT architectures.

You will work on ATPG, SCAN, JTAG and other techniques, collaborate with Analog, Digital and Testing teams, and contribute to silicon bring-up and failure analysis. Strong Verilog/SystemVerilog skills and ASIC tool experience are required.