DFT ASIC & SoC Engineer — Test & Validation

Oesía Group; Rivas-Vaciamadrid; On-site; EUR 60,000 - 85,000; Full time

Job summary

Grupo Oesía is seeking an experienced DFT/SoC engineer to join a multidisciplinary team. You will design, develop and integrate test solutions for ASICs and SoCs, contributing to high-value projects across strategic sectors.

The role requires 3+ years in DFT, knowledge of ATPG/MBIST/LBIST and experience with Cadence/Synopsys. ARM and RISC-V familiarity are highly valued, along with collaboration across design, verification and physical teams.

Qualifications

• Bachelor's or Master's degree in Electronic Engineering, Telecommunications Engineering, Industrial Engineering or a related field.
• At least 3 years of experience in DFT (Design for Test) for ASICs or SoCs.
• Knowledge of scan insertion, ATPG, MBIST and/or LBIST.
• Experience with EDA tools (Cadence, Synopsys).
• Highly valued: experience in complete ASIC development cycles, silicon validation and bring-up, and knowledge of ARM, RISC-V and SoC architectures.
• Projects with real technological impact.
• Teams where sharing knowledge is part of the way we work.
• Continuous professional development tailored to each profile and individual.
• An environment where engineering and people move forward together.

Responsibilities

• Design and implement Design for Test (DFT) strategies for ASIC circuits and SoC systems.
• Develop test and diagnostic structures for integrated circuits, such as scan chains, MBIST or LBIST.
• Participate in test pattern generation and validation activities (ATPG).
• Collaborate with design, verification and physical implementation teams.
• Analyse coverage metrics and optimise test solutions throughout the development process.
• Support silicon validation and manufacturing activities.

Skills

DFT for ASICs/SoCs

ATPG

MBIST

LBIST

Design for Test

ARM/RISC-V knowledge

Education

Bachelor’s or Master’s in Electronic/Telecommunications/Industrial Engineering

Tools

Cadence

Synopsys

Job description

Grupo Oesía is seeking an experienced DFT/SoC engineer to join a multidisciplinary team. You will design, develop and integrate test solutions for ASICs and SoCs, contributing to high-value projects across strategic sectors.

The role requires 3+ years in DFT, knowledge of ATPG/MBIST/LBIST and experience with Cadence/Synopsys. ARM and RISC-V familiarity are highly valued, along with collaboration across design, verification and physical teams.