Mid DFT Engineer – Hybrid Barcelona, Test & Yield

Hireroo Ltd; Barcelona; Híbrido; EUR 65.000 - 90.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Hybrid work

4 days in office, 1 day remote

Relocation support

Housing search assistance

Visa support

Private medical insurance

Virtual shares

Language classes

Tax support

Annual leave 25 days

€150 monthly food allowance

Descripción de la vacante

Hireroo Ltd. in Barcelona, Spain, seeks a Mid-level DFT Engineer to drive DFT architectures and production-ready test strategies for complex SoC/SiP designs. You will collaborate across design, validation, packaging and EDA vendors to boost testability, yield and efficiency.

The role involves working across pre- and post-silicon stages with Tessent/SSN expertise, focusing on scalable test solutions and continuous process improvements, with hybrid work in Barcelona.

Formación

• 4+ years of DFT, silicon test or related semiconductor experience.
• Tessent and SSN experience.
• Experience integrating Tessent or SSN methods with advanced node EDA flows.
• Experience with SoC or SiP tape outs.
• Strong understanding of scan chains, BIST and JTAG.
• DFT architecture and implementation experience.
• Post silicon test optimization and yield analysis.
• Experience defining production test strategies.
• Understanding of silicon characterization and test coverage.
• SystemVerilog and Verilog.
• Shell, Tcl or Python scripting.
• Ability to work across design, validation and manufacturing teams.
• Bachelor, Master or PhD in Electrical Engineering, Computer Engineering or related field.

Responsabilidades

• Define and implement DFT architectures
• Insert and validate scan chains, BIST and JTAG
• Support DFT integration across SoC and SiP designs
• Develop silicon, package and system level test strategies
• Develop automated production and characterization test solutions
• Improve test coverage, test time, cost and production efficiency
• Support post silicon test optimization, silicon debug and yield analysis
• Work with design and validation teams to resolve DFT related issues
• Collaborate with packaging, operations, IP providers and EDA vendors
• Contribute to DFT methodology and process improvements
• Support production readiness and test quality through development and ramp

Conocimientos

4+ years DFT experience

SystemVerilog

Verilog

Shell

Tcl

Python scripting

Educación

Bachelor/Master/PhD in Electrical or Computer Engineering

Herramientas

Tessent

SSN

EDA flows

Descripción del empleo

Hireroo Ltd. in Barcelona, Spain, seeks a Mid-level DFT Engineer to drive DFT architectures and production-ready test strategies for complex SoC/SiP designs. You will collaborate across design, validation, packaging and EDA vendors to boost testability, yield and efficiency.

The role involves working across pre- and post-silicon stages with Tessent/SSN expertise, focusing on scalable test solutions and continuous process improvements, with hybrid work in Barcelona.