Senior Physical Design Engineer - Hybrid, Growth & Training

Capgemini; Gaià; Hybride; EUR 70 000 - 90 000; Plein temps

Avantages offerts par ce poste

Hybrid work

Health and life insurance

Referral bonuses

Training and certifications

Career growth programs

Résumé du poste

Capgemini Engineering is seeking a Senior Physical Design Engineer to drive physical design activities from floorplanning through sign-off and tape-out on advanced technology nodes. You will lead CTS, routing, power planning, and timing closure for large ASICs and work with multi-disciplinary teams across design stages.

The ideal candidate has 6+ years of ASIC physical design experience, proficiency with Synopsys/Cadence tools, strong scripting skills, and hands-on experience with ECO generation

Qualifications

• Bachelor’s or Master’s degree in Electrical or Computer Engineering.
• 6+ years of experience in Physical Design or ASIC implementation.
• Experience with 10nm and below technology nodes.
• Experience with large designs (500K–1M+ instances).
• Proficient with Synopsys and/or Cadence PD and timing tools.
• Strong floorplanning, power planning, placement, CTS, routing, and optimization.
• Knowledge of synthesis flows and DFT scan insertion and coverage.
• Strong STA, signal integrity, and timing closure.
• Experience with ECO generation and sign-off.
• EM/IR, DRC, LVS, Antenna, and ERC familiarity.
• Sign-off and tape-out activities.
• Scripting in Perl, TCL, Python, Makefile.
• Top-level floorplanning and pin assignment is a plus.
• Good English communication skills.

Responsabilités

• Perform block and full-chip Physical Design using advanced technology nodes.
• Carry out floorplanning, partitioning, power planning, placement, CTS, routing, and optimization.
• Lead timing analysis and timing closure; manage signal integrity and noise analysis.
• Generate and implement functional and timing ECOs.
• Perform physical verification: Formal Verification, EM/IR, DRC, LVS, Antenna, and ERC analysis and fixes.
• Work on Low Power design implementation and related methodologies.
• Develop scripts for clock skew analysis, critical path analysis, I/O interfaces, and constraint budgeting.
• Support sign-off and tape-out activities.
• Collaborate with multidisciplinary teams through design implementation and closure.

Connaissances

Floorplanning

Power planning

Placement

CTS

Routing

Design optimization

Scripting

EM/IR

DFT scan

DRC

LVS

Antenna

ERC

Timing analysis

STA

Sign-off

Tape-out

English communication

Formation

Bachelor's or Master's in Electrical/Computer Engineering

Outils

Synopsys tools

Cadence tools

Description du poste

Capgemini Engineering is seeking a Senior Physical Design Engineer to drive physical design activities from floorplanning through sign-off and tape-out on advanced technology nodes. You will lead CTS, routing, power planning, and timing closure for large ASICs and work with multi-disciplinary teams across design stages.

The ideal candidate has 6+ years of ASIC physical design experience, proficiency with Synopsys/Cadence tools, strong scripting skills, and hands-on experience with ECO generation