DFT Engineer - Mid

Hireroo Ltd; Barcelona; Híbrido; EUR 65.000 - 90.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Hybrid work

4 days in office, 1 day remote

Relocation support

Housing search assistance

Visa support

Private medical insurance

Virtual shares

Language classes

Tax support

Annual leave 25 days

€150 monthly food allowance

Descripción de la vacante

Hireroo Ltd. in Barcelona, Spain, seeks a Mid-level DFT Engineer to drive DFT architectures and production-ready test strategies for complex SoC/SiP designs. You will collaborate across design, validation, packaging and EDA vendors to boost testability, yield and efficiency.

The role involves working across pre- and post-silicon stages with Tessent/SSN expertise, focusing on scalable test solutions and continuous process improvements, with hybrid work in Barcelona.

Formación

• 4+ years of DFT, silicon test or related semiconductor experience.
• Tessent and SSN experience.
• Experience integrating Tessent or SSN methods with advanced node EDA flows.
• Experience with SoC or SiP tape outs.
• Strong understanding of scan chains, BIST and JTAG.
• DFT architecture and implementation experience.
• Post silicon test optimization and yield analysis.
• Experience defining production test strategies.
• Understanding of silicon characterization and test coverage.
• SystemVerilog and Verilog.
• Shell, Tcl or Python scripting.
• Ability to work across design, validation and manufacturing teams.
• Bachelor, Master or PhD in Electrical Engineering, Computer Engineering or related field.

Responsabilidades

• Define and implement DFT architectures
• Insert and validate scan chains, BIST and JTAG
• Support DFT integration across SoC and SiP designs
• Develop silicon, package and system level test strategies
• Develop automated production and characterization test solutions
• Improve test coverage, test time, cost and production efficiency
• Support post silicon test optimization, silicon debug and yield analysis
• Work with design and validation teams to resolve DFT related issues
• Collaborate with packaging, operations, IP providers and EDA vendors
• Contribute to DFT methodology and process improvements
• Support production readiness and test quality through development and ramp

Conocimientos

4+ years DFT experience

SystemVerilog

Verilog

Shell

Tcl

Python scripting

Educación

Bachelor/Master/PhD in Electrical or Computer Engineering

Herramientas

Tessent

SSN

EDA flows

Descripción del empleo

Job Description

Our partner is looking for a DFT Engineer to support DFT implementation, test development and production readiness for complex SoC and SiP designs.

You will work across pre silicon and post silicon stages, collaborating with design, validation, packaging, operations, external IP providers and EDA vendors. The role focuses on improving testability, manufacturability, test coverage, yield and production quality across advanced semiconductor programs.

Level: Mid
Location: Barcelona, Spain, Hybrid

Responsibilities

• Define and implement DFT architectures

• Insert and validate scan chains, BIST and JTAG

• Support DFT integration across SoC and SiP designs

• Develop silicon, package and system level test strategies

• Develop automated production and characterization test solutions

• Improve test coverage, test time, cost and production efficiency

• Support post silicon test optimization, silicon debug and yield analysis

• Work with design and validation teams to resolve DFT related issues

• Collaborate with packaging, operations, IP providers and EDA vendors

• Contribute to DFT methodology and process improvements

• Support production readiness and test quality through development and ramp

Requirements

• 4+ years of DFT, silicon test or related semiconductor experience

• Tessent and SSN experience

• Experience integrating Tessent or SSN methods with advanced node EDA flows

• Experience with SoC or SiP tape outs

• Strong understanding of scan chains, BIST and JTAG

• DFT architecture and implementation experience

• Post silicon test optimization and yield analysis

• Experience defining production test strategies

• Understanding of silicon characterization and test coverage

• SystemVerilog and Verilog

• Shell, Tcl or Python scripting

• Ability to work across design, validation and manufacturing teams

• Bachelor, Master or PhD in Electrical Engineering, Computer Engineering or related field

Preferred / Valued Knowledge

• RISC V architecture, especially within SoC, RTL, verification, DFT, Physical Design, firmware, software, PCIe, DDR or related hardware environments

• Experience with advanced semiconductor nodes

• Production test and high volume manufacturing exposure

• Experience improving DFT methodology, test cost or yield

• Familiarity with chiplet based designs

What’s in it for you?

Our partner offers an opportunity to work on advanced semiconductor programs in Barcelona, with strong technical ownership and career growth.

• 4 days per week in the Barcelona office, 1 day from home

• Flexible working hours

• 1 week per year working from anywhere

• 25 days annual leave plus December 24 and 31

• €150 monthly food allowance

• Private medical insurance

• Relocation support

• Housing search assistance

• Visa support where required

• Relocation support for family

• Virtual shares

• Language classes

• Tax support, subject to eligibility