Senior DFT Engineer – Avnet ASIC Israel (AAI) - Remote (Europe)

COMMIT Offshore; España; Remote; EUR 70,000 - 110,000; Full time

Job summary

COMMIT Offshore in Spain seeks a Senior DFT Engineer to own the end-to-end Design-for-Test flow for customer SoCs, from architecture through tape-out and production test hand-off. You will drive architecture, implementation, scan insertion, ATPG, MBIST, JTAG, and fault models, with gate-level simulation and formal verification.

Perl/Tcl and UNIX scripting are required, and advanced-node experience is a plus.

Qualifications

• BSc in Electrical Engineering is required.
• 3+ years hands-on DFT experience preferred.
• Strong knowledge of scan, ATPG, MBIST, JTAG and fault models.
• Experience with Synopsys DFT Compiler/TestMAX or Siemens Tessent.
• Gate-level simulation, formal verification, Perl/Tcl, and UNIX.

Responsibilities

• Develop and implement DFT architecture, scan insertion, and ATPG.
• Handle memory BIST, boundary scan, and at-speed testing.
• Debug DFT rule violations and improve test coverage.
• Run gate-level simulations and pattern validation.
• Perform formal equivalence checking and automate flows using scripting.
• Own the end-to-end DFT process through tape-out and production.

Skills

DFT architecture

Scan insertion

ATPG

MBIST

JTAG

Fault models

Gate-level sim

Formal verification

Perl scripting

Tcl scripting

UNIX

Education

BSc in Electrical Engineering

Tools

Synopsys DFT Compiler/TestMAX

Siemens Tessent

Job description

The company is looking for a Senior DFT Engineer to own Design-for-Test (DFT) for customer SoCs, from architecture and implementation through tape-out and production test hand-off.

Responsibilities:

• Develop and implement DFT architecture, scan insertion, and ATPG.
• Handle memory BIST, boundary scan, and at-speed testing.
• Debug DFT rule violations and improve test coverage.
• Run gate-level simulations and pattern validation.
• Perform formal equivalence checking and automate flows using scripting.
• Own the end-to-end DFT process through tape-out and production.

Requirements:

• BSc in Electrical Engineering.
• Minimum 3 years of hands-on DFT experience.
• Strong knowledge of scan, ATPG, MBIST, JTAG, and fault models.
• Experience with Synopsys DFT Compiler/TestMAX or Siemens Tessent.
• Experience with gate-level simulation, formal verification, Perl/Tcl, and UNIX.
• End-to-end DFT flow ownership. Nice to have: Advanced-node experience (7nm and below), Siemens Tessent ScanPro/TestKompress/LBIST, and Python scripting.