Senior SoC Physical Design Architect: Tape-out Lead

Aion Silicon Ltd; Barcelona; On-site; EUR 150,000 - 190,000; Full time

Job summary

Aion Silicon Ltd seeks a seasoned Principal Engineer for SoC Physical Design to lead complex ASIC/SoC implementations from architecture to tape-out. You will drive full-chip physical design, floorplanning, power/clock planning, PMU strategies, and signoff, collaborating across Architecture, RTL, Verification, DFT, STA, Packaging, and Silicon Validation teams.

Ideal candidates bring 15+ years of ASIC/SoC PD experience, a proven tape-out record, and deep expertise in 22nm and below nodes,

Qualifications

• 15+ years of ASIC/SoC Physical Design experience.
• Proven tape-out track record for SoC/ASIC projects.
• Strong understanding of floorplanning, clock & power distribution, global signal planning, I/O planning and hard IP integration.
• Experience with multi-voltage and multi-clock domain SoCs, ESD strategies, mixed-signal integration, and package-aware design.

Responsibilities

• Lead full-chip physical design from architecture through tape-out.
• Drive methodology, signoff, and execution across teams (Architecture, RTL, Verification, DFT, STA, Packaging).
• Define milestones, track progress, manage dependencies and ensure on-time tape-out.
• Coordinate with STA, DFT, RTL, Verification, Power Integrity, and Packaging teams to meet goals.
• Troubleshoot design, flow, and methodology issues; mentor engineers and improve flows.

Skills

Leadership

SoC Integration

Tape-outs

Cross-functional work

Mentoring

Education

B.Tech / M.Tech in Electrical Engineering or related

Tools

Calibre

IC Validator (ICV)

Pegasus

RedHawk

Voltus

PrimePower

TCL

Perl

Python

Job description

Aion Silicon Ltd seeks a seasoned Principal Engineer for SoC Physical Design to lead complex ASIC/SoC implementations from architecture to tape-out. You will drive full-chip physical design, floorplanning, power/clock planning, PMU strategies, and signoff, collaborating across Architecture, RTL, Verification, DFT, STA, Packaging, and Silicon Validation teams.

Ideal candidates bring 15+ years of ASIC/SoC PD experience, a proven tape-out record, and deep expertise in 22nm and below nodes,