Power Integrity Engineer - EMIR & PDN Signoff

Aion Silicon Ltd; Barcelona; On-site; EUR 90,000 - 120,000; Full time

Job summary

Aion Silicon Ltd is seeking an EMIR / Power Integrity Engineer to join the SoC Physical Design team in Barcelona. You will lead PDN planning, PDN optimization, EMIR verification, and signoff for advanced semiconductor designs.

Responsibilities include IR drop analyses, EM analysis, ECO implementation, and signoff-driven improvements. You will collaborate with PD, CAD, RTL, Package, and Reliability teams and automate flows with Tcl, Python, Perl, or Shell scripting.

Qualifications

• Experience with EMIR signoff methodologies and CAD automation.
• Strong knowledge of PDN, EM, IRDrop, and power integrity.
• Familiarity with packaging parasitics and power delivery architecture.
• Ability to develop signoff methodologies and automation flows.
• Excellent debugging and analytical skills.

Responsibilities

• Perform Power Integrity and EMIR analysis for complex SoC designs.
• Develop, analyze, and optimize PDNs to meet power and reliability targets.
• Execute Static and Dynamic IR Drop and EM analysis across design cycles.
• Define simulation setups and signoff criteria for PI verification.
• Enhance EMIR analysis flows with timing, package, and board abstractions.
• Identify and root-cause EM/IR/EMI violations; implement ECOs.
• Provide ECO solutions to improve power grid, decap insertion, and routing.
• Validate ECO effectiveness via iterative EMIR analysis and signoff closure.
• Collaborate with Physical Design, CAD, RTL, Package, and Reliability teams.
• Automate flows for analysis, debugging, and reporting using scripting.

Skills

EMIR analysis

Power Integrity

PDN design

Scripting

Debugging

Communication

Education

Bachelors/Masters in Electrical Engineering

Tools

Cadence Voltus

Ansys RedHawk/RedHawk-SC

Synopsys PrimeRail/PrimePower

Cadence Innovus

Synopsys ICC2

FC_SHELL

Tcl, Python, Perl, Shell scripting

Job description

Aion Silicon Ltd is seeking an EMIR / Power Integrity Engineer to join the SoC Physical Design team in Barcelona. You will lead PDN planning, PDN optimization, EMIR verification, and signoff for advanced semiconductor designs.

Responsibilities include IR drop analyses, EM analysis, ECO implementation, and signoff-driven improvements. You will collaborate with PD, CAD, RTL, Package, and Reliability teams and automate flows with Tcl, Python, Perl, or Shell scripting.