Senior Physical Design Engineer: RTL-to-GDSII & Timing

Analog Devices; Valencia; Presencial; EUR 60.000 - 90.000; Jornada completa

Descripción de la vacante

Analog Devices, Inc. is seeking a Senior Physical Design Engineer to own end-to-end physical implementation and signoff of digital blocks and SoCs in Valencia. You will collaborate with a distributed engineering team to deliver high-quality RTL-to-GDSII results and drive design closure.

You should have hands-on experience with Cadence or Synopsys flows, and a strong background in timing, DRC/LVS, and floorplanning. Excellent communication and ownership are required.

Formación

• 3–7 years of physical design or digital implementation experience.
• Hands-on with Cadence or Synopsys physical design flows.
• B.Tech./M.Tech. or equivalent in Electrical or Electronics Engineering.

Responsabilidades

• Execute RTL-to-GDSII implementation activities, including floor-planning, CTS, routing, timing closure and physical verification.
• Use Cadence or Synopsys based flows to support implementation, optimisation and signoff.
• Apply knowledge of synthesis and timing constraints to review results and provide feedback.
• Analyze and resolve timing, power, IR/EM, DRC and LVS issues with guidance from seniors.
• Communicate effectively and take ownership of assigned tasks.

Conocimientos

RTL-to-GDSII implementation

Timing closure

Problem solving

Teamwork

Educación

B.Tech./M.Tech. or equivalent in Electrical/Electronics Engineering

Herramientas

Cadence

Synopsys

Descripción del empleo

Analog Devices, Inc. is seeking a Senior Physical Design Engineer to own end-to-end physical implementation and signoff of digital blocks and SoCs in Valencia. You will collaborate with a distributed engineering team to deliver high-quality RTL-to-GDSII results and drive design closure.

You should have hands-on experience with Cadence or Synopsys flows, and a strong background in timing, DRC/LVS, and floorplanning. Excellent communication and ownership are required.