Principal STA & Constraints Signoff Architect

Aion Silicon Ltd; Barcelona; On-site; EUR 120,000 - 150,000; Full time

Job summary

Aion Silicon Ltd in Barcelona is seeking a Principal STA/Constraints Sign-Off Engineer to lead timing signoff and constraint methodology development for advanced-node SoC and IP designs. You will drive signoff closure across SDCs, MMMC, and ECOs while enabling tape-outs with optimal performance, power, and area.

You will collaborate with Architecture, RTL, Verification, DFT and PD teams, mentoring engineers and developing automation to streamline flows.

Qualifications

• 12+ years of STA, timing signoff, and ASIC/SoC implementation.
• Hands-on expertise in PrimeTime, SDC development, MMMC analysis, timing closure.
• In-depth knowledge of advanced-node signoff requirements and PDK libraries.
• Strong Tcl, Python, or Perl scripting for flow automation.
• Excellent debugging, analytical, and technical leadership skills.
• Experience with advanced-node technologies (7nm/5nm/3nm and below).
• Familiarity with UPF, low-power signoff flows and high-speed IPs (PCIe, DDR, UCIE).

Responsibilities

• Own and drive timing signoff methodologies across SoC/IP blocks.
• Develop, review, and validate SDC constraints, timing exceptions, and MMMC signoff environments.
• Lead setup, hold, SI, OCV/AOCV/POCV, and timing closure activities through final signoff.
• Drive timing correlation across synthesis, implementation, extraction, and signoff flows.
• Support ECO closure, low-power timing analysis, and cross-functional signoff activities.
• Develop automation scripts, methodology documentation, training materials, and best practices.
• Collaborate closely with RTL, Physical Design, DFT, CAD, Verification, and IP teams to achieve timing convergence.

Skills

STA expertise

Signoff leadership

Automation scripting

Team mentoring

Timing signoff

Cross-functional collaboration

Education

BS/MS in Electrical Engineering

Tools

PrimeTime

ICC2/Fusion Compiler

StarRC

ICV

Tempus

Innovus

Voltus

Job description

Aion Silicon Ltd in Barcelona is seeking a Principal STA/Constraints Sign-Off Engineer to lead timing signoff and constraint methodology development for advanced-node SoC and IP designs. You will drive signoff closure across SDCs, MMMC, and ECOs while enabling tape-outs with optimal performance, power, and area.

You will collaborate with Architecture, RTL, Verification, DFT and PD teams, mentoring engineers and developing automation to streamline flows.