Sr. Staff/Principal Synthesis and STA Lead OBO

Eliyan; Toronto, Vancouver; On-site; CAD 120,000 - 150,000; Full time

Job summary

A leading chiplet startup in Toronto is seeking an experienced Synthesis and STA Lead to create innovative synthesis methodologies for high-performance chiplet systems. The ideal candidate will have over 12 years of experience in high-speed design and STA closure, alongside a strong education background in Electrical Engineering. Responsibilities include developing a flexible synthesis framework, managing STA sign-off processes, and collaborating with cross-functional teams. The startup offers a dynamic work environment with excellent benefits.

Benefits

Excellent benefits

Fun work environment

Qualifications

• 12+ years of experience in high-speed design synthesis and STA closure.
• Expertise in timing closure of various functional and test modes.
• Hands-on experience with ASIC timing constraints generation and validation.

Responsibilities

• Create a highly flexible synthesis framework supporting multiple process technology nodes.
• Work closely with design and DFT teams for scalable constraint methodology.
• Responsible for STA sign-off and generation of timing sign-off ECOs.

Skills

High-speed design synthesis

STA closure

Scripting (Tcl, Perl, Python)

Problem solving

Communication skills

Education

Bachelors or Masters or Ph.D in Electrical Engineering

Tools

PT

Tempus

Job description

Join the leading chiplet startup! As an Eliyan Synthesis and STA lead, you will be working at a fast‑paced early‑stage startup creating technologies that fuel tomorrow’s chiplet based systems with best‑in‑class power, area, manufacturability, and design flexibility. You will be responsible for putting together synthesis and STA methodologies for best‑in‑class PHYs and Controllers. You will work with a cross‑functional team of experts that operate from first principles, innovate and push the envelope to create high‑volume and high‑performance manufacturable products. We offer a fun work environment with excellent benefits.

Key Responsibilities:

• Responsible for creation of a highly flexible synthesis framework supporting multiple process technology nodes, block, chip specific customizations, wire‑load, physical‑aware synthesis and flexible choice of EDA tools
• Create dashboards for early architectural and implementation explorations for ease of comparison (PPA)
• Work closely with design and DFT teams to define a scalable, hierarchical constraints methodology that supports various mission, test modes & scenarios
• Work closely with physical implementation teams to define the optimal MMMC corners for various stages of implementation vis‑à‑vis placement, CTS and routing
• Responsible for putting together an STA sign‑off document per process node per foundry
• Responsible for STA sign‑off, generation of timing sign‑off ECOs that implementation teams can incorporate
• Responsible for debugging complex constraint issues or timing challenges during implementation
• Define an effective strategy to achieve high throughput of PNR and ECO cycles
• Champion the functional ECO implementation methodology
• Manage the LEC methodology, tool choice and mapping constraints required for block and chip level
• Manage the UPF/CPF flow for synthesis including timing methodologies with level‑shifter and isolation cells as necessary

Qualifications:

• Bachelors or Masters or Ph.D in Electrical Engineering and related fields, or equivalent
• 12+ years of experience in high‑speed design synthesis and STA closure
• Hands‑on experience with ASIC timing constraints generation, constraints validation (3rd‑party tools), and timing closure
• Expertise and advanced knowledge of industry standard timing tools (PT, Tempus)
• Strong understanding and experience in timing closure of various functional and test modes
• Expertise in deep‑submicron process and impact on timing vis‑à‑vis noise glitch, OCV, IR‑STA, crosstalk
• Proficient in scripting (Tclk, Perl, Python)
• Proven track record of being a highly visible contributor as part of a start‑up like environment
• Problem solver and efficient in written/verbal communication – excellent data organization skills and churns high quality work product
• Ability to work cross‑functionally with digital and analog design, DFT, implementation teams