Senior Physical Design Engineer - SoC PPA & Timing Expert

Ciena Corporation

Ottawa

Hybrid

CAD 109,000 - 174,000

Full time

4 days ago

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Benefits offered by this job

Medical, dental, and vision plans

RRSP/DCPP with company matching

Employee Stock Purchase Program (ESPP)

Paid holidays and leave

Job summary

Ciena Corporation in Ottawa is seeking a Senior Physical Design Engineer to drive physical implementation of large mixed-signal SoC ASICs targeting advanced nodes. You will lead placement, routing, power grid design, clock distribution, and signoff quality through PPA-focused optimization.

Collaborate with RTL and analog teams, run STA and timed ECOs, explore trade-offs, and write scripts to automate backend flows.

Qualifications

Bachelor's degree in Electrical or Computer Engineering or related field with significant ASIC physical digital design experience.
Experience in timing closure for submicron backend flows and trade-offs.

Responsibilities

Define physical architecture and roadmap for large mixed-signal SoCs.
Collaborate with RTL designers and layout engineers for floorplanning, power grids, and clock distribution.
Perform Place & Route trials, implement timing ECOs, and address RTL fixes as needed.
Run STA, analyze timing reports, and resolve P&R vs STA correlation issues.
Write scripts to automate backend flows and collaborate with tool vendors for improvements.