Senior ASIC Physical Design Engineer - Tapeout Lead

Socket.dev; Toronto; On-site; CAD 173,000 - 243,000; Full time

Job summary

Qualcomm Canada ULC in Toronto is seeking an experienced ASIC Physical Designer to lead end-to-end PD for complex SoCs and retimer ASICs. You will drive floorplanning, CTS, placement & routing, PDN, and timing closure, while coordinating with front-end, analog, DFT, packaging, and silicon validation teams.

The role requires a strong leadership mindset and hands-on expertise with IR/EM, CTS, and large-scale integration.

Qualifications

• Master’s degree in Electrical/Computer Engineering with 3+ years of ASIC PD experience, or Bachelor's with 4+ years in ASIC PD.
• Strong experience with end-to-end ASIC PD flow and timing closure.
• Hands-on with EDA tools Cadence Innovus or Synopsys ICC2.
• Solid understanding of IR/EM, CTS, and large-scale SoC integration.

Responsibilities

• Lead and drive end-to-end Physical Design flow for SoC/retimer ASICs, including floorplanning, CTS, placement & routing, PDN, and timing closure.
• Plan and implement full-chip or hierarchical designs with full-reticle-scale integration.
• Collaborate with cross-functional teams to ensure design convergence and tapeout readiness.
• Lead integration of high-speed SerDes macros and mixed-signal IP, ensuring robust floorplan and signal integrity.

Skills

End-to-end PD flow

Timing closure

Physical verification

EDA tools: Innovus

Power integrity

CTS / clocking

SoC integration

SerDes / retimer

Multi-die / chiplet

Python / Tcl scripting

Education

Master's degree in Electrical/Computer Engineering

Bachelor's degree in Science/Engineering

PhD in Science/Engineering

Tools

Cadence Innovus

Synopsys ICC2

Job description

Qualcomm Canada ULC in Toronto is seeking an experienced ASIC Physical Designer to lead end-to-end PD for complex SoCs and retimer ASICs. You will drive floorplanning, CTS, placement & routing, PDN, and timing closure, while coordinating with front-end, analog, DFT, packaging, and silicon validation teams.

The role requires a strong leadership mindset and hands-on expertise with IR/EM, CTS, and large-scale integration.