Senior Physical Design Engineer

European Tech Recruit; Ottawa; On-site; CAD 150,000 - 190,000; Full time

Job summary

European Tech Recruit is seeking a Senior Physical Design Engineer to own backend implementation from netlist to GDSII across complex ASIC blocks. The role involves advanced physical design flows on FinFET nodes and collaboration with an experienced team to deliver designs to closure.

You will run PrimeTime, perform IR-drop analysis, and optimize PPA while coordinating with analog, front-end, and other teams to meet timing and area goals.

Qualifications

• 8+ years of experience in ASIC digital physical design / place & route.
• Hands-on experience with Synopsys and Cadence tools and flows.
• Experience with FinFET nodes, DRC rules and P&R needs.
• Strong floorplanning and physical implementation expertise.
• Solid understanding of CTS and clock design for timing closure.
• Experience with IR-drop analysis and optimization.
• PT-ECO or Tweaker experience a plus.
• Strong scripting and automation skills.
• Experience with Synthesis, StarRC, PrimeTime DMSA, RedHawk, Calibre, LEC, or Formality.
• Self-motivated, proactive team player.

Responsibilities

• Own place & route implementation and analyze physical design results.
• Develop effective floorplans to support physically-aware synthesis.
• Drive designs through timing closure and physical verification.
• Debug issues across EDA tools, timing constraints, DFT, and RTL/design implementation.
• Collaborate with front-end design teams to improve RTL quality and implementation efficiency.
• Implement timing ECOs and optimize designs for performance.
• Run PrimeTime and analyze timing reports.
• Develop strategies to optimize power, performance, and area (PPA).
• Perform IR-drop analysis and implement optimization strategies.
• Collaborate with analog, front-end, and other physical design teams to align objectives.

Skills

ASIC physical design

Place & route

Timing closure

Scripting & automation

Tools

Synopsys

Cadence

PrimeTime

StarRC

Calibre

LEC

Formality

Job description

We are looking for a Senior Physical Design Engineer to join a growing engineering team in Ottawa. In this role you would take ownership of backend implementation from netlist through to GDSII across challenging ASIC blocks and sub-systems.

You will work with advanced physical design flows and single-digit FinFET technology nodes, collaborating with an experienced engineering team to deliver complex designs through to successful closure.

This is a fully remote senior-level position, open to candidates based anywhere.

Key Responsibilities

• Own place & route implementation and analyze physical design results.
• Develop effective floorplans to support physically-aware synthesis.
• Drive designs through timing closure and physical verification.
• Debug issues across EDA tools, timing constraints, DFT, and RTL/design implementation.
• Work closely with front-end design teams to improve RTL quality and implementation efficiency.
• Implement timing ECOs and optimize designs for performance.
• Run PrimeTime and analyze timing reports.
• Develop strategies to optimize power, performance, and area (PPA).
• Perform IR-drop analysis and implement optimization strategies.
• Collaborate with analog, front-end, and other physical design teams to align implementation objectives.

Key Qualifications

• 8+ years of experience in ASIC digital physical design / place & route.
• Strong hands-on experience with leading Synopsys and Cadence EDA tools and flows.
• Experience working with advanced FinFET technology nodes, including DRC rules and node-specific P&R requirements.
• Strong practical experience in floorplanning and physical implementation.
• Solid understanding of Clock Tree Synthesis (CTS) and clock design for timing closure.
• Experience with IR-drop analysis and optimization.
• Strong background in timing closure and ECO implementation; PT-ECO or Tweaker experience is a plus.
• Strong scripting and automation skills.
• Experience with several of the following: synthesis, StarRC, PrimeTime DMSA, RedHawk, Calibre, LEC, or Formality.
• A self-motivated, proactive approach with the ability to work effectively both independently and as part of a collaborative engineering team.