Senior ASIC RTL Design Engineer

European Recruitment BV; Ottawa; On-site; CAD 120,000 - 160,000; Full time

Job summary

European Recruitment BV is seeking experienced Verification engineers in Ottawa to work on leading-edge ASIC projects for North American clients. You will translate architectural requirements into synthesizable SystemVerilog/Verilog, owning blocks from spec through front-end sign-off, with a focus on power, performance and physical implementation.

You will collaborate with architecture, RTL, firmware, DV, and PD teams to deliver complex, high-performance silicon and meet project milestones with

Qualifications

• 10+ years hands-on ASIC RTL design experience
• Strong SystemVerilog and Verilog skills; translate specs into RTL
• Experience with high-bandwidth datapaths, pipelining and multi-clock design
• Experience integrating complex IP + high-speed interfaces (PCIe, Ethernet, die-to-die)
• Strong CDC/RDC, reset sequencing, assertions, and static checks
• Synthesis, timing constraints, timing-report analysis; coordinate with physical design
• Scripting in Python/Tcl to automate design flows
• Ability to own technical decisions, lead reviews, communicate risks clearly

Responsibilities

• Define block microarchitecture, interfaces, and latency/performance budgets
• Develop configurable static-switch fabrics, protocol multiplexers, datapaths
• Integrate protocol and PHY IP including clocking, reset, status interfaces
• Implement CSR access, configuration sequencing, interrupts with firmware
• Develop assertions and resolve lint, CDC, RDC findings
• Create timing constraints, analyse synthesis results with PD teams on timing closure
• Implement low-power controls, UPF usage, and DFT integration
• Collaborate with verification to debug design issues and document work clearly
• Deliver RTL and synthesis handoffs aligned with milestones

Skills

ASIC RTL design

SystemVerilog/Verilog

High-speed interfaces

CDC/RDC/Assertions

Synthesis & timing

Scripting (Python/Tcl)

Technical leadership/ownership

Tools

Python

Tcl

Job description

Our client, a North American ASIC Services provider is looking for experienced Verification engineers to join their growing team in Ottawa to work on various Design projects for semiconductor clients across North America.

The I/O chiplet connects die-to-die interfaces with multi-protocol, high-speed I/O, combining UCIe, PCIe, Ethernet, static switching, and an embedded management subsystem.

You will work closely with architecture, RTL, verification, firmware, physical design, and IP teams to deliver complex, high-performance silicon.

Client identity and detailed programme specifications will be shared confidentially during the interview process.

You will translate architectural requirements into synthesizable SystemVerilog and Verilog, taking ownership of assigned blocks from specification through front-end sign-off.

The role combines custom datapath and control logic with the integration of third-party protocol and PHY IP, with a strong focus on power, performance, area, and physical implementation.

Key Responsibilities

• Define block microarchitecture, interface specifications, and measurable latency, throughput, and resource budgets.
• Develop configurable static-switch fabrics, protocol multiplexers, pipelined datapaths, and boundary rate-adaptation logic.
• Configure and integrate protocol and PHY IP, including clocking, reset, status, and control interfaces.
• Implement CSR access, configuration sequencing, interrupts, and management logic in collaboration with the firmware team.
• Develop assertions and resolve lint, CDC, RDC, and connectivity findings.
• Develop timing constraints, analyse synthesis results, and work closely with physical design teams on partitioning, congestion, and timing closure.
• Implement low-power controls and support power-intent checks, DFT integration, and formal equivalence activities.
• Debug design issues alongside verification engineers and maintain clear, accurate design documentation.
• Deliver reviewed RTL and synthesis handoffs in line with project milestones and front-end sign-off requirements.

Must-Have Qualifications

• 10+ years of hands-on ASIC RTL design experience, with ownership through successful tape-out.
• Strong SystemVerilog and Verilog skills, with proven ability to translate specifications into clear, maintainable RTL.
• Strong experience with high-bandwidth datapaths, pipelining, multiplexing, and multi-clock design.
• Practical experience integrating complex IP and working with at least one high-speed interface such as PCIe, Ethernet, or die-to-die interconnect.
• Strong understanding of CDC/RDC, reset sequencing, assertions, and static design checks.
• Hands-on experience with synthesis, timing constraints, and timing-report analysis, with the ability to work with physical design teams to resolve issues.
• Scripting experience using Python, Tcl, or similar languages to automate design flows.
• Ability to take ownership of technical decisions, lead design reviews, and communicate risks, challenges, and progress clearly.

Nice-to-Have Experience

• UCIe or other chiplet interconnect experience, including protocol-to-PHY integration and advanced packaging considerations.
• PCIe Gen6/Gen7, 200G Ethernet, or 224G PAM4 SerDes integration experience.
• Experience delivering advanced-node ASICs, implementing low-power designs using UPF, or developing physically aware RTL partitions.
• Experience with embedded RISC-V subsystems, AXI/APB, secure boot, sideband management, or FPGA prototyping.