Senior Digital ASIC Physical Design Engineer: Optimize PPA

Ciena; Ottawa; On-site; CAD 109,000 - 174,000; Full time

Job summary

Ciena in Ottawa seeks a Digital ASIC Physical Implementation Engineer to shape large mixed-signal SoC designs for WaveLogic. You will drive the backend flow from netlist to GDSII, partnering with RTL and layout teams to optimize floorplans, power grids, and clock networks for best PPA.

We seek hands-on backend expertise, scripting for automation, and practical knowledge of UPF/SOCV/POCV, Calibre, and STA tools to ensure timing closure across complex designs.

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering or related field with significant ASIC design experience.
• Strong backend ASIC flow knowledge including timing/power/area trade-offs.
• Proven experience using Place&Route tools.
• Ability to write scripts to automate backend tasks.
• Understanding of UPF and SOCV/POCV concepts.

Responsibilities

• Define physical architecture and manage flow from netlist to GDSII using EDA tools.
• Collaborate with RTL designers and layout engineers for floorplans and power grids.
• Tune EDA tool settings to achieve signoff-quality PPA.
• Propose optimizations to reduce power and increase performance.
• Integrate analog blocks with ASIC/SoC teams.
• Conduct initial Place & Route trials and refine design for correlation.
• Generate timing ECOs and functional ECOs as needed.
• Use Formality or Conformal for formal verification and analyze reports.

Skills

ASIC physical design

Timing closure

PPA optimization

Scripting/automation

RTL collaboration

Education

Bachelor degree in Electrical or Computer Engineering

Tools

Place&Route tools

Calibre

Formal verification tools

Conformal

Formality

STA tools

Job description

Ciena in Ottawa seeks a Digital ASIC Physical Implementation Engineer to shape large mixed-signal SoC designs for WaveLogic. You will drive the backend flow from netlist to GDSII, partnering with RTL and layout teams to optimize floorplans, power grids, and clock networks for best PPA.

We seek hands-on backend expertise, scripting for automation, and practical knowledge of UPF/SOCV/POCV, Calibre, and STA tools to ensure timing closure across complex designs.