Senior Layout Design Manager, High-Speed Analog CMOS

Ciena Corporation; Ottawa; Hybrid; CAD 171,000 - 273,000; Full time

Job summary

Ciena Corporation in Ottawa seeks a Senior Manager of Layout Design to lead advanced analog high-speed layouts for BiCMOS/CMOS technologies. You will coordinate cross-team efforts, mentor junior designers, and drive template-based layout methodologies to high-performance outputs.

You will oversee feasibility studies, ensure design-rule compliance, and push for efficient, scalable layout processes across global partners, while delivering MPWs and production chips.

Qualifications

• 15+ years of layout experience.
• Experience leading analog high-speed layout design within BiCMOS/CMOS technologies.
• Deliver MPWs, test chips, and product chips with proven results.
• Understand challenging design rules from leading-edge processes.

Responsibilities

• Lead Block and Macro level layout development including floor-planning and optimization.
• Plan and schedule projects to ensure successful delivery with work–life balance.
• Mentor junior team members and co-op students.
• Automate layout flows with scripts and pcells.

Skills

Lead layout design

Project planning

Mentoring juniors

Strong communication

Self-starter

Education

Bachelor's degree in electrical or computer engineering, computer science, or in a related field

Tools

Cadence

Mentor Graphics

Synopsys

Virtuoso

Calibre

Job description

Ciena Corporation in Ottawa seeks a Senior Manager of Layout Design to lead advanced analog high-speed layouts for BiCMOS/CMOS technologies. You will coordinate cross-team efforts, mentor junior designers, and drive template-based layout methodologies to high-performance outputs.

You will oversee feasibility studies, ensure design-rule compliance, and push for efficient, scalable layout processes across global partners, while delivering MPWs and production chips.