Senior ASIC Physical Design Lead for SoC Tapeouts

Qualcomm; Toronto; On-site; CAD 124,000 - 174,000; Full time

Job summary

Qualcomm Canada ULC is seeking a senior ASIC Physical Design engineer to lead end‑to‑end PD flows for SoCs and retimers. You will collaborate with front‑end, analog/SerDes, DFT, and packaging teams to drive tapeouts and ensure design convergence.

The role requires strong experience with CTS, DRC/LVS, and access to Cadence Innovus or Synopsys ICC2, plus scripting in Python or Tcl to automate flows.

Qualifications

• Master's or Bachelor's with 3+ years of ASIC PD experience or related field.
• Experience with end-to-end ASIC PD flow and signoff methodologies.
• Hands-on with DRC/LVS, DFM/DFY for tapeouts.

Responsibilities

• Lead end-to-end PD flow for SoC and retimer ASICs, including floorplanning, CTS, placement, routing, PDN, and timing closure.
• Plan full‑chip or hierarchical designs and drive timing closure across corners and modes.
• Perform and review PD verification (DRC, LVS, DFM, DFY).
• Collaborate with front‑end, analog/SerDes, DFT, packaging, and silicon validation teams to ensure tapeout readiness.
• Lead integration of high‑speed SerDes macros and mixed-signal IP with robust floorplanning and SI alignment.
• Drive IR/EM closure, power optimization, congestion mitigation for large die designs; provide schedules and risk assessments.

Skills

End-to-end ASIC PD flow

Timing closure

Physical verification flows

Cadence Innovus

Synopsys ICC2

Power delivery (IR/EM)

CTS / clocking architectures

SoC integration challenges

SerDes/retimer designs

Full-reticle SoC implementation

Multi-die / chiplet / advanced packing

Python

Tcl

Education

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Tools

Cadence Innovus

Synopsys ICC2

Job description

Qualcomm Canada ULC is seeking a senior ASIC Physical Design engineer to lead end‑to‑end PD flows for SoCs and retimers. You will collaborate with front‑end, analog/SerDes, DFT, and packaging teams to drive tapeouts and ensure design convergence.

The role requires strong experience with CTS, DRC/LVS, and access to Cadence Innovus or Synopsys ICC2, plus scripting in Python or Tcl to automate flows.