ASIC Physical Design Engineer — Power-Efficient AI SoCs

Movellus Inc.; Toronto; Hybrid; CAD 110,000 - 150,000; Full time

Benefits offered by this job

Stock options

Medical, dental, vision coverage

Retirement plan

Hybrid work in Markham

Job summary

Movellus Inc. is seeking an experienced ASIC Physical Design Engineer to own the RTL-to-GDSII flow, including synthesis, PNR, STA, power/EMIR analysis, DFT insertion and physical verification. You will work with RTL designers to resolve timing issues and optimize power while contributing to tapeout-ready designs.

You will collaborate with architects, verification teams, and post-silicon engineers to refine CAD flows and ensure robust silicon realization in a hybrid Markham, Canada office.

Qualifications

• Bachelor's or Master's in Electrical Engineering or related field.
• Minimum 4 years of relevant ASIC implementation experience.
• Solid knowledge of RTL-to-GDSII flow including synthesis, PNR, STA, power/EMIR, DFT, LVS/DRC.

Responsibilities

• Own RTL-to-GDSII flow stages — synthesis, PNR, STA, IR-drop, EM analysis, DFT, and physical verification (DRC/LVS).
• Perform STA at design-flow stages and fix timing violations with RTL designers.
• Analyze power/EMIR reports and optimize power grid/rail sign-off.
• Generate and validate timing constraints (SDC) and support RTL synthesis.
• Review synthesis, PNR, STA, and power/EMIR reports to refine CAD flow.
• Document implementation strategies, analyses, and best practices.
• Collaborate with architects, RTL engineers, verification and post-silicon teams.

Skills

RTL design (SystemVerilog)

Synthesis/PNR/STA

Power/EMIR analysis

DFT insertion

Physical verification (LVS/DRC)

Python/TCL scripting

Teamwork & communication

Education

Bachelor's or Master's in Electrical Engineering

Tools

Synopsys Design Compiler/ICC2/Custom Compiler

Cadence Genus/Innovus/Virtuoso

PrimeTime

Ansys RedHawk-SC

Cadence Genus/Innovus

Job description

Movellus Inc. is seeking an experienced ASIC Physical Design Engineer to own the RTL-to-GDSII flow, including synthesis, PNR, STA, power/EMIR analysis, DFT insertion and physical verification. You will work with RTL designers to resolve timing issues and optimize power while contributing to tapeout-ready designs.

You will collaborate with architects, verification teams, and post-silicon engineers to refine CAD flows and ensure robust silicon realization in a hybrid Markham, Canada office.