Senior High-Speed AMS IC Designer (Hybrid, Ottawa)

Cisco; Ottawa; Hybrid; CAD 204,000 - 275,000; Full time

Job summary

Cisco is seeking a seasoned Mixed-Signal IC Design Engineer in Ottawa to design, lay out, and validate high-speed AMS circuits for optical communications products. You will architect, design, layout, measure and productize ultra-deep sub-micron CMOS designs with speeds >25Gb/s and high accuracy, collaborating with RF, DSP, and packaging teams.

You will mentor junior engineers, lead a block on a complex chip, and ensure signal integrity through design reviews and production handoffs in a dynamic

Qualifications

• Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience.
• Experience in design, simulation and measurement of high speed ICs in at least 3 of the areas listed.

Responsibilities

• Lead a large block on a complex chip, mentor team members and track deliverables.
• Participate in peer review of complex IC designs and provide solid design methodology from conception to production.
• Collaborate with packaging and hardware design teams to ensure signal and power integrity specifications are met.
• Develop high speed AMS circuits and best-in-class products that push boundaries of possible.
• Collaborate with cross-functional teams and learn from colleagues in a team-oriented environment.

Skills

High-Speed IC design

Serial links

PLL design

Clock distribution

Op-amps

Equalization techniques

Mentoring

Education

Bachelor's degree in related field

Master's degree

PhD

Tools

Cadence (Virtuoso)

Spectre/APS/SpectreX

Layout tools (Virtuoso)

Calibre

EMX

MATLAB

Job description

Cisco is seeking a seasoned Mixed-Signal IC Design Engineer in Ottawa to design, lay out, and validate high-speed AMS circuits for optical communications products. You will architect, design, layout, measure and productize ultra-deep sub-micron CMOS designs with speeds >25Gb/s and high accuracy, collaborating with RF, DSP, and packaging teams.

You will mentor junior engineers, lead a block on a complex chip, and ensure signal integrity through design reviews and production handoffs in a dynamic