Senior Digital Verification Engineer: RTL & UVM Lead

Cadence; Toronto; On-site; CAD 85,000 - 110,000; Full time

Job summary

A leading technology firm is seeking a Lead Verification Engineer in Toronto to ensure high-quality digital RTL verification and develop reusable verification components. The successful candidate will contribute to various verification activities and must possess a Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science. Familiarity with SystemVerilog, UVM, and scripting languages is preferred. The role involves collaboration across teams and requires full-time presence in the Toronto office, with minimal travel expectations.

Qualifications

• Bachelor's degree in engineering or computer science is required.
• Experience with UVM and digital design flow is essential.
• Familiarity with various communication protocols is a plus.

Responsibilities

• Verify digital RTL and develop reusable verification components.
• Contribute to verification flows, test planning, and execution.
• Collaborate effectively with design and verification teams.

Skills

Understanding of verification architecture and methodologies

Understanding of Metric Driven Verification

Understanding of Universal Verification Methodologies (UVM)

Understanding of functional coverage planning and checks

Understanding of SystemVerilog Assertions (SVAs)

Understanding of digital design flow

Experience with scripting languages (Python, Perl, Ruby, Sed, Awk)

Education

Bachelor of Science in Electrical Engineering, Computer Engineering, or Computer Science

Master of Science in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Cadence tools

Job description

A leading technology firm is seeking a Lead Verification Engineer in Toronto to ensure high-quality digital RTL verification and develop reusable verification components. The successful candidate will contribute to various verification activities and must possess a Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science. Familiarity with SystemVerilog, UVM, and scripting languages is preferred. The role involves collaboration across teams and requires full-time presence in the Toronto office, with minimal travel expectations.