Staff Engineer, Physical Design/Implementation Toronto, Ontario, Canada ASICS Engineering

Qualcomm; Toronto; On-site; CAD 173,000 - 243,000; Full time

Job summary

Qualcomm Canada ULC is seeking a lead for physical design implementation of complex retimer-class and full-reticle ASICs in advanced technology nodes. You will lead end-to-end PD flow, including floorplanning, CTS, placement & routing, PDN, and timing closure.

Collaborate with cross-functional teams to drive integration of high-speed SerDes/macros, ensure tapeout readiness, and optimize IR/EM/power for large-scale die designs. Strong technical leadership is required.

Qualifications

• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 3+ years of ASIC Physical Design experience, OR Bachelor’s with 4+ years, OR PhD with 2+ years.

Responsibilities

• Lead end-to-end Physical Design flow for SoC and retimer ASICs (floorplanning, CTS, placement & routing, PDN, timing closure).
• Plan and implement full-chip/hierarchical designs including full-reticle-scale integration.
• Drive timing closure across corners/modes and SI-aware optimization.
• Perform/lead physical verification checks (DRC, LVS, DFM, DFY).
• Collaborate with front-end, analog/SerDes, DFT, packaging, and silicon validation teams for tapeout readiness.
• Lead integration of high-speed SerDes macros and mixed-signal IP with robust floorplanning.
• Drive IR/EM closure, power optimization, and congestion mitigation for large dies.
• Provide schedules, risk assessment, and execution tracking for silicon tapeouts.
• Contribute in design reviews and aid architecture/implementation decisions.
• Develop/improve physical design methodologies and flows for efficiency.

Skills

End-to-end PD flow

Timing closure

Physical verification

EDA tools

Power integrity

CTS/Clocking

SoC integration

SerDes/retimer familiarity

Education

Master’s in Electrical/Computer Engineering/CS

Bachelor’s in Electrical/Computer Engineering/CS

PhD in relevant field

Tools

Cadence Innovus

Synopsys ICC2

Job description

Company:

Qualcomm Canada ULC

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.

You will lead and drive physical design implementation for complex, large-scale retimer-class and full-reticle ASIC products in advanced technology nodes. This role requires strong technical leadership to synthesize ambiguous requirements, drive execution across cross-functional teams, and deliver high-quality silicon meeting aggressive power, performance, and area (PPA) targets. Replacement Position

What You'll Do

• Lead and execute end-to-end Physical Design flow for SoC and retimer ASICs, including:
  • Floorplanning
  • Clock Tree Synthesis (CTS)
  • Placement & Routing
  • Power Delivery Network (PDN)
  • Timing analysis and closure
• Plan and implement full-chip or hierarchical designs, including full-reticle-scale integration
• Drive timing closure across all corners and modes (MMMC), including SI‑aware optimization
• Perform and review physical verification checks:
  • DRC, LVS
  • Design‑for‑manufacturability (DFM)
  • Design‑for‑yield (DFY)
• Collaborate with cross‑functional engineering teams (front‑end, analog/SerDes, DFT, packaging, silicon validation) to ensure design convergence and tapeout readiness
• Lead integration of high‑speed SerDes macros and mixed‑signal IP, ensuring robust floorplan and signal integrity alignment
• Drive IR/EM closure, power optimization, and congestion mitigation for large die designs
• Provide schedules, risk assessment, and execution tracking to drive successful silicon tapeouts
• Act as a strong technical contributor in design reviews and project meetings, influencing architecture and implementation decisions
• Develop and improve physical design methodologies and flows to enhance efficiency and scalability

What You’ll Need

• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of experience, OR
  Bachelor’s degree AND 4+ years of progressive experience in ASIC Physical Design or related domain
• Strong experience with:
  • End‑to‑end ASIC Physical Design flow
  • Timing closure and signoff methodologies
  • Physical verification flows
• Hands‑on expertise in industry‑standard EDA tools (e.g., Cadence Innovus / Synopsys ICC2)
• Solid understanding of:
  • Power delivery and reliability (IR/EM)
  • Clocking architectures and CTS
  • Large‑scale SoC integration challenges

Preferred Qualifications

• Experience with high‑speed SerDes / retimer designs (PAM4‑class signaling)
• Experience with full‑reticle or near-reticle SoC implementation
• Familiarity with multi‑die / chiplet / advanced packaging architectures
• Exposure to data center, networking, or optical connectivity ASICs
• Strong scripting and automation skills (Python, Tcl)

Key Competencies

• Proven ability to lead complex PD execution in high‑pressure tapeout environments
• Strong analytical and problem‑solving skills with attention to detail
• Ability to synthesize ambiguous or conflicting requirements into execution plans
• Effective collaboration across global, cross‑functional engineering teams

Minimum Qualifications

• • Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
• OR
  Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• OR
  PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

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Pay range and Other Compensation & Benefits:

$124,200.00 - $174,200.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play.