Staff Engineer, Physical Design/Implementation

Qualcomm; Toronto; On-site; CAD 124,000 - 174,000; Full time

Job summary

Qualcomm Canada ULC is seeking a senior ASIC Physical Design engineer to lead end‑to‑end PD flows for SoCs and retimers. You will collaborate with front‑end, analog/SerDes, DFT, and packaging teams to drive tapeouts and ensure design convergence.

The role requires strong experience with CTS, DRC/LVS, and access to Cadence Innovus or Synopsys ICC2, plus scripting in Python or Tcl to automate flows.

Qualifications

• Master's or Bachelor's with 3+ years of ASIC PD experience or related field.
• Experience with end-to-end ASIC PD flow and signoff methodologies.
• Hands-on with DRC/LVS, DFM/DFY for tapeouts.

Responsibilities

• Lead end-to-end PD flow for SoC and retimer ASICs, including floorplanning, CTS, placement, routing, PDN, and timing closure.
• Plan full‑chip or hierarchical designs and drive timing closure across corners and modes.
• Perform and review PD verification (DRC, LVS, DFM, DFY).
• Collaborate with front‑end, analog/SerDes, DFT, packaging, and silicon validation teams to ensure tapeout readiness.
• Lead integration of high‑speed SerDes macros and mixed-signal IP with robust floorplanning and SI alignment.
• Drive IR/EM closure, power optimization, congestion mitigation for large die designs; provide schedules and risk assessments.

Skills

End-to-end ASIC PD flow

Timing closure

Physical verification flows

Cadence Innovus

Synopsys ICC2

Power delivery (IR/EM)

CTS / clocking architectures

SoC integration challenges

SerDes/retimer designs

Full-reticle SoC implementation

Multi-die / chiplet / advanced packing

Python

Tcl

Education

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Tools

Cadence Innovus

Synopsys ICC2

Job description

Company

Qualcomm Canada ULC

Job Area

Engineering Group, Engineering Group > ASICS Engineering

General Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next‑generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.

Replacement Position

What You'll Do

• Lead and execute end‑to‑end Physical Design flow for SoC and retimer ASICs, including:
  • Floorplanning
  • Clock Tree Synthesis (CTS)
  • Placement & Routing
  • Power Delivery Network (PDN)
  • Timing analysis and closure
• Plan and implement full‑chip or hierarchical designs, including full‑reticle‑scale integration
• Drive timing closure across all corners and modes (MMMC), including SI‑aware optimization
• Perform and review physical verification checks:
  • DRC, LVS
  • Design‑for‑manufacturability (DFM)
  • Design‑for‑yield (DFY)
• Collaborate with cross‑functional engineering teams (front‑end, analog/SerDes, DFT, packaging, silicon validation) to ensure design convergence and tapeout readiness
• Lead integration of high‑speed SerDes macros and mixed‑signal IP, ensuring robust floorplan and signal integrity alignment
• Drive IR/EM closure, power optimization, and congestion mitigation for large die designs
• Provide schedules, risk assessment, and execution tracking to drive successful silicon tapeouts
• Act as a strong technical contributor in design reviews and project meetings, influencing architecture and implementation decisions
• Develop and improve physical design methodologies and flows to enhance efficiency and scalability

What You'll Need

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of experience, OR Bachelor's degree and 4+ years of progressive experience in ASIC Physical Design or related domain
• Strong experience with:
  • End‑to‑end ASIC Physical Design flow
  • Timing closure and signoff methodologies
  • Physical verification flows
• Hands‑on expertise in industry‑standard EDA tools (e.g., Cadence Innovus / Synopsys ICC2)
• Solid understanding of:
  • Power delivery and reliability (IR/EM)
  • Clocking architectures and CTS
  • Large‑scale SoC integration challenges

Preferred Qualifications

• Experience with high‑speed SerDes / retimer designs (PAM4‑class signaling)
• Experience with full‑reticle or near‑reticle SoC implementation
• Familiarity with multi‑die / chiplet / advanced packaging architectures
• Exposure to data center, networking, or optical connectivity ASICs
• Strong scripting and automation skills (Python, Tcl)

Key Competencies

• Proven ability to lead complex PD execution in high‑pressure tapeout environments
• Strong analytical and problem‑solving skills with attention to detail
• Ability to synthesize ambiguous or conflicting requirements into execution plans
• Effective collaboration across global, cross‑functional engineering teams

Minimum Qualifications

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Applicants

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability‑[e-mail] or call Qualcomm's toll‑free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay Range And Other Compensation & Benefits

$124,200.00 - $174,200.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer.

If you would like more information about this role, please contact Qualcomm Careers.