ASIC Physical Design Engineer: DSP Core Tapeout

Qualcomm; Markham; On-site; CAD 90,000 - 135,000; Full time

Job summary

Qualcomm Canada ULC in Markham, Ontario is seeking a Physical Design Engineer to contribute to DSP cores used in next‑generation mobile, compute, and AI products. In this role, you will gain hands‑on exposure to the complete ASIC development cycle, from RTL handoff through physical implementation and tapeout.

This position is ideal for early‑career engineers with a strong foundation in VLSI and digital design fundamentals who are passionate about semiconductor technology and eager to build

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field.
• 6 months to 2 years of ASIC Physical Design, Digital Design, or related semiconductors.
• Strong understanding of VLSI, digital design fundamentals and timing analysis.
• Familiarity with RTL to GDSII flow and ASIC design methodologies.
• Experience with EDA tools for synthesis, timing analysis, or verification.
• Basic scripting skills in Python, Tcl, Perl, or Shell.

Responsibilities

• Contribute to ASIC Physical Design activities from netlist to GDSII under senior guidance.
• Support floorplanning, placement, clock tree synthesis, routing, timing, and sign‑off tasks.
• Analyze and debug timing, congestion, and design rule issues.
• Participate in PPA analysis and optimization efforts.
• Assist with ECO implementation, design closure, and tapeout readiness.
• Collaborate with RTL, DFT, verification, and methodology teams to resolve challenges.
• Develop scripts and automation to improve productivity and design quality.

Skills

ASIC

Physical Design

VLSI

Digital Design

Scripting

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

EDA tools

Synthesis

Timing analysis

CTS / Floorplanning

Python/Tcl scripting

Job description

Qualcomm Canada ULC in Markham, Ontario is seeking a Physical Design Engineer to contribute to DSP cores used in next‑generation mobile, compute, and AI products. In this role, you will gain hands‑on exposure to the complete ASIC development cycle, from RTL handoff through physical implementation and tapeout.

This position is ideal for early‑career engineers with a strong foundation in VLSI and digital design fundamentals who are passionate about semiconductor technology and eager to build