Principal Analog IC Design Engineer

Qualcomm; Toronto; In loco; CAD 160.000 - 230.000; Tempo pieno

Descrizione del lavoro

Qualcomm Canada ULC is seeking an engineer to oversee design, verification, and documentation of CMOS analog/mixed-signal blocks such as data converters, PLLs, and ADCs. You’ll participate from system definition through layout and silicon evaluation, using Cadence and MATLAB, with emphasis on high performance and reliability in a collaborative team.

The candidate should hold a PhD/MSc/BSc in Electrical Engineering and bring 6–8+ years of ASIC experience, including transistor-level design and

Competenze

• PhD/MSc/BSc with ASIC design, verification, or related experience as stated in the ad.
• Experience with transistor-level circuit design using advanced CMOS nodes.
• Familiarity with SPICE and Verilog-A for analog behavioural modeling.

Mansioni

• Collaborate with world-class engineers to meet design goals.
• Ensure analog block performance adheres to specifications.
• Refine circuit implementations to optimize power, performance, and area.
• Propose design and verification strategies for high-quality results.
• Oversee layout to minimize parasitics and variation impacts.
• Present simulation data for peer review.
• Document design features and key testbench performance metrics.

Conoscenze

Excellent communication skills

Detail-oriented

Analytical and problem-solving skills

Self-motivated and self-managing

Team collaboration and listening

Formazione

PhD in Engineering Science or Electrical and Computer Engineering

MSc in Engineering Science or Electrical and Computer Engineering

BSc in Electrical Engineering or related field

Strumenti

Cadence

SPICE

MATLAB

Verilog/VHDL

EDA tools for schematic/layout/verification

Descrizione del lavoro

Qualcomm Canada ULC is seeking an engineer to oversee design, verification, and documentation of CMOS analog/mixed-signal blocks such as data converters, PLLs, and ADCs. You’ll participate from system definition through layout and silicon evaluation, using Cadence and MATLAB, with emphasis on high performance and reliability in a collaborative team.

The candidate should hold a PhD/MSc/BSc in Electrical Engineering and bring 6–8+ years of ASIC experience, including transistor-level design and