Senior ASIC Physical Design Lead

Nutanix; Toronto; On-site; CAD 124,000 - 174,000; Full time

Job summary

Qualcomm Canada ULC is seeking a Senior ASIC Physical Design Engineer to lead end-to-end physical design flow for complex SoC and retimer ASICs, driving floorplanning, CTS, placement, routing and signoff to meet aggressive PPA targets.

You will collaborate with front-end, analog/SerDes, DFT, packaging and validation teams to ensure tapeout readiness, perform timing analysis, and optimize power delivery while managing schedules and risk throughout large-die implementations.

Qualifications

• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 3+ years of ASIC PD experience or
• Bachelor’s degree with 4+ years of progressive ASIC PD experience
• PhD in Science, Engineering, or related field with 2+ years of ASIC PD experience

Responsibilities

• Lead end-to-end ASIC Physical Design flow for SoC and retimer ASICs, including floorplanning, CTS, placement & routing, and PDN.
• Drive timing closure across corners and modes and ensure tapeout readiness with SI-aware optimizations.
• Perform and review physical verification checks (DRC/LVS) and DFY/DFM considerations; collaborate with cross-functional teams.

Education

Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Bachelor’s degree in Science, Engineering, or related field with 4+ years of experience

PhD in Science, Engineering, or related field with 2+ years of experience

Tools

Cadence Innovus

Synopsys ICC2

Python

Tcl

Job description

Qualcomm Canada ULC is seeking a Senior ASIC Physical Design Engineer to lead end-to-end physical design flow for complex SoC and retimer ASICs, driving floorplanning, CTS, placement, routing and signoff to meet aggressive PPA targets.

You will collaborate with front-end, analog/SerDes, DFT, packaging and validation teams to ensure tapeout readiness, perform timing analysis, and optimize power delivery while managing schedules and risk throughout large-die implementations.