Senior Physical Design Engineer - Low-Power SoCs

Qualcomm; Toronto; On-site; CAD 124,000 - 174,000; Full time

Benefits offered by this job

Discretionary bonus program

RSU grants

Benefits package

Job summary

Qualcomm Canada ULC is seeking an experienced ASIC Engineer to define, model, design, optimize, verify, validate, implement, and document IP development for high-performance, low-power products. The role collaborates across teams to determine product execution paths in a replacement position.

You will drive backend flow, floorplanning, power planning, PPA optimization, and signoff processes, leveraging LLM/EDA tools for optimization and ensuring timing closure and physical verification.

Qualifications

• Bachelor's degree in Electrical or Computer Engineering or related field.
• 2+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field.

Responsibilities

• Drive the backend process through the entire implementation flow.
• Floor-planning/ Block Partitioning /Power Planning.
• Support Front-End team in performing PPA optimization trials.
• Leverage LLM and EDA tools to drive PPA optimization.
• Place & Route with special focus on power and area optimization.
• Clock Tree Synthesis/Inspection/Optimization.
• Static timing verification and timing closure experience.
• Perform physical verification and fixing (DRC, ANT, DFM, LVS, ERC,…)
• Perform EM/IR signoff and address power integrity issues.

Skills

Physical Design

ASIC design

Verification

IP development

Low-Power designs

Floorplanning

Power Planning

Education

Bachelor's degree in Electrical or Computer Engineering or related field

Master's degree in Science or Engineering

PhD in Science or Engineering

Job description

Qualcomm Canada ULC is seeking an experienced ASIC Engineer to define, model, design, optimize, verify, validate, implement, and document IP development for high-performance, low-power products. The role collaborates across teams to determine product execution paths in a replacement position.

You will drive backend flow, floorplanning, power planning, PPA optimization, and signoff processes, leveraging LLM/EDA tools for optimization and ensuring timing closure and physical verification.