Senior ASIC Physical Design Lead – Fullchip

105 Cisco Systems Canada Co.; Vancouver; On-site; CAD 225,000 - 326,000; Full time

Job summary

Cisco Systems Canada Co. in Vancouver is seeking a seasoned Physical Design engineer to lead fullchip floorplanning, IP placement, clock planning, and signoff methodologies.

You will collaborate across RTL/DFT/EDA teams to optimize timing, power integrity, and die size while leveraging AI tools to boost productivity. The role requires deep experience with RTL-to-GDSII flows, hierarchical design, and close interaction with foundries and IP vendors to ensure robust signoff.

Qualifications

• Bachelors + 12 years experience or Masters + 8 or PhD + 5 years
• Engineering with 3+ years Physical Design experience
• Experience on Fullchip activities
• RTL2GDSII flow and tapeouts in 7nm/5nm/3nm or below
• Experience with Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre/Pegasus

Responsibilities

• Fullchip floorplan and IP placement
• Collaborate with RTL/DFT/EDA teams for requirements
• Hierarchical implementation flow including clock plan and bump planning
• Hands-on Fullchip clock mesh and H-Tree methods
• RTL-to-GDSII: floorplan, power grid, place and route, timing, SI, PV
• Analyze tool flows; identify efficiency gaps and improvements
• Work with RTL, DFT, implementation, EDA vendors to improve design methodology
• Proficiency in low-power design using UPF
• Define signoff methodologies with foundry and validate with Post-Silicon teams
• Use AI tools to improve productivity

Skills

Fullchip floorplan

RTL to GDSII

Clock mesh

Flex-HTree

Timing analysis

Power integrity

Physical verification

EDA tools

Signoff methodologies

AI productivity

Foundry collaboration

Low-power UPF

Education

Bachelor’s/Master’s/PhD in Engineering

Tools

Innovus

Tempus/Primetime

Redhawk/Voltus

Calibre/Pegasus

Job description

Cisco Systems Canada Co. in Vancouver is seeking a seasoned Physical Design engineer to lead fullchip floorplanning, IP placement, clock planning, and signoff methodologies.

You will collaborate across RTL/DFT/EDA teams to optimize timing, power integrity, and die size while leveraging AI tools to boost productivity. The role requires deep experience with RTL-to-GDSII flows, hierarchical design, and close interaction with foundries and IP vendors to ensure robust signoff.