Tile PnR Lead - SoC Physical Design & Tapeout

Advanced Micro Devices; Markham; Hybrid; CAD 120,000 - 150,000; Full time

Benefits offered by this job

Benefits at a glance

Job summary

Advanced Micro Devices (AMD) in Markham, ON is seeking an experienced Tile Place & Route Lead to drive the physical implementation of complex SoC tiles from floorplan through tapeout. You will lead strategy, planning, and mentored teams across global programs to ensure design quality and on-time delivery.

The ideal candidate will have proven leadership across multiple tape-outs at advanced nodes and strong expertise in Tile PnR, timing, and power optimization, collaborating with Architecture,

Qualifications

• Proven leadership across multiple projects or product families.
• Multiple successful tape-outs at advanced technology nodes.
• Experience leading critical tiles or IPs.
• Expertise in congestion analysis, timing architecture, power optimization and PPA improvement.

Responsibilities

• Lead physical implementation of complex SoC tiles from floorplan through tapeout.
• Drive Tile PnR strategy including floorplanning, placement, CTS, routing, timing closure, congestion management, IR/EM closure, and sign-off readiness.
• Define implementation methodologies and best practices to improve PPA and design quality.
• Lead root-cause analysis and resolution of complex implementation challenges.
• Coordinate with Design, Timing, CAD, Methodology, Full Chip Floorplan, Power, and Verification teams.

Skills

Tile PnR leadership

Physical design expertise

Mentorship & team leadership

Education

BS/MS in Electrical or Computer Engineering

Tools

ICC2

Fusion Compiler

PrimeTime

Calibre

RedHawk/Totem

Job description

Advanced Micro Devices (AMD) in Markham, ON is seeking an experienced Tile Place & Route Lead to drive the physical implementation of complex SoC tiles from floorplan through tapeout. You will lead strategy, planning, and mentored teams across global programs to ensure design quality and on-time delivery.

The ideal candidate will have proven leadership across multiple tape-outs at advanced nodes and strong expertise in Tile PnR, timing, and power optimization, collaborating with Architecture,