Physical ASIC Design Implementation Engineer

Imec; Vlaams-Brabant; Remote; EUR 90,000 - 140,000; Full time

Job summary

Imec in Leuven is seeking a Physical ASIC Design Implementation Engineer to drive the full Cadence Innovus place-and-route flow for advanced nodes (12–5nm). You will work directly with customers and the Back-End team to deliver tape-outs, including floorplanning, power grid design, and timing closure.

Candidates hold a Master in Electronics with at least 8 years in physical implementation, experience with UPF, STA, clock-tree synthesis, DRC/ERC/LVS, and strong English communication in

Qualifications

• Master's degree in Electronics is required.
• 8+ years of experience in physical implementation in advanced nodes (12–5nm) and hierarchical designs.
• Experience with power reduction techniques such as gated clocks, voltage domains, memory retention and power-down domains.
• Experience debugging any tool/flow/design issue.
• Excellent communication skills in English and ability to work in an international team.
• Able to interact with customers.

Responsibilities

• Set up the Cadence Innovus Place & Route flow for the specific libraries and foundry node used.
• Set up low power design (UPF).
• Floorplanning and power grid design.
• Detailed Timing Driven Placement.
• STA and timing optimization for setup.
• Clock Tree Synthesis.
• Scan chain re-stitching.
• Detailed Timing Driven Route (incl. SI).
• In-place optimization (IPO) to achieve timing in all corners.
• Resolve setup and hold violations.
• Sign-off extraction (SPEF/QUANTUS).
• Sign-off timing (TEMPUS).
• Sign-off Power analysis (VOLTUS).
• Physical verification (DRC, ERC, LVS, ANT).
• Logic equivalence check.
• Lead hierarchical design partitioning and coordinate sub-block timing budgets.

Skills

Power reduction techniques

Debugging

Communication skills

Customer interaction

English proficiency

Education

Master Degree in Electronics

Tools

Cadence Innovus

TEMPUS

VOLTUS

DRC/ERC/LVS/ANT

Job description

Physical ASIC Design Implementation Engineer

What you will do

For more than 25 years, imec has been offering anASIC prototyping and production service to worldwide companies. Imec helps itscustomers to design their integrated circuits (chips) and bring them from theprototype to the production stage. Our list of customers includes more than 900universities and companies worldwide. For the further extension of the physicaldigital implementation group (Back-End group) in DSRD, we are looking for ahighly motivated engineer.

DSRD, as part of imec, has an extensive industrialexperience, contacts with leading industrial foundries, and long-standingrelationships with all the main EDA tool vendors and IP providers. This unitsupports worldwide customers in the layout, prototype, fabrication and test ofadvanced electronic products.

As Physical ASIC design engineerwithin DSRD, you will be in direct contact with our customers for futureprojects. You will have full understanding of the complete Cadence InnovusPlace&Route flow:

• Set up the flow for the specific libraryset and foundry node used
• Set up low power design (UPF)
• Floorplanning & power grid design
• Detailed Timing Driven Placement
• STA & possible design optimisationfor setup
• Clock Tree Synthesis
• Scan chain re-stitching
• Detailed Timing Driven Route (incl. SI)
• IPO’s (in-place optimization) to get thetiming in all corners correct
• Solve setup & hold violations
• Sign-off extraction (SPEF/QUANTUS)
• Sign-off timing (TEMPUS)
• Sign-off Power analysis (VOLTUS)
• Physical verification (DRC, ERC, LVS,ANT)
• Logic equivalent check

Forhierarchical designs you can take the lead for partitioning and split the toplevel SDC file into timing budget requirements/constraints of the sub-blocks.You will work directly with the Physical Design implementation team during theentire chip design cycle to drive signoff closure for tape-out, You arealso the technical voice to the customer to discuss his specifications.

What we do for you

We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its office in Leuven. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will define the society of tomorrow.

We are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth.

We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits.

Who you are

• You have a Master Degree in Electronics
• You have at least 8 years of experience in physicalimplementation in advanced nodes (12 – 5nm) and hierarchicaldesigns.
• You have experience in power reductiontechniques like gated clocks, voltage domains, memory retention and switchoff power domains.
• You have experience in debugging any tool/flow/designissue.
• You have excellent communication skills(English is a must) and can work within an international team.
• You like to interact with customers.

IMEC and its affiliates will not accept unsolicited resumes from any source other than directly from a candidate. IMEC will consider unsolicited referrals and/or resumes submitted by vendors such as search firms, staffing agencies, professional recruiters, fee-based referral services and recruiting agencies (hereafter “Agency”) to have been referred by the Agency free of charge. IMEC will not pay a fee to any Agency that does not have a prior written agreement with IMEC, validated by its HR department, in place regarding a specific job opening and allowing to submit resumes.