Principal Physical Design Engineer – SoC & IP Leader

Nalys; Vlaams-Brabant; On-site; EUR 120,000 - 180,000; Full time

Job summary

Nalys is seeking a Principal Physical Design Engineer to lead advanced SoC/IP physical design from RTL to GDSII, including floorplanning, power integrity, P&R, CTS, and STA. You will drive low-power strategies and standardize flows.

You will mentor engineers, optimize design methodologies, and evaluate next‑gen EDA tools to boost efficiency and quality in a fast-paced semiconductor environment. Jointly with architecture and verification teams, you will solve complex technical challenges.

Qualifications

• Minimum 15 years in ASIC physical design with tape-out records.
• Expertise in floorplanning, place & route, clocking and STA.
• Strong problem-solving and leadership in a fast-paced team environment.

Responsibilities

• Lead physical design from RTL to GDSII.
• Own floorplanning, power distribution, P&R, and clock tree synthesis/STA.
• Collaborate with architecture/verification teams to ensure robust implementations.
• Mentor engineers and drive design methodologies and automation.

Skills

ASIC physical design

Tape-out experience

EDA tool proficiency

Scripting (Tcl/Perl/Python)

P&R and STA knowledge

DFM knowledge

Education

Bachelor's or Master’s in EE/Electrical Engineering

Tools

Cadence Innovus/Tempus

Synopsys Fusion Compiler/PrimeTime

Ansys RedHawk/PathFinder

Job description

Nalys is seeking a Principal Physical Design Engineer to lead advanced SoC/IP physical design from RTL to GDSII, including floorplanning, power integrity, P&R, CTS, and STA. You will drive low-power strategies and standardize flows.

You will mentor engineers, optimize design methodologies, and evaluate next‑gen EDA tools to boost efficiency and quality in a fast-paced semiconductor environment. Jointly with architecture and verification teams, you will solve complex technical challenges.