Senior Physical Design Engineer

Nalys Group; Vlaams-Brabant; On-site; EUR 120,000 - 180,000; Full time

Job summary

Nalys Group is seeking a Principal Physical Design Engineer for a major semiconductor client in Belgium. You will own the physical implementation from RTL to GDSII, focusing on floor planning, placing and routing, clock tree synthesis, and STA, while driving low-power strategies and automation improvements.

You will mentor engineers, lead design methodologies, and collaborate with cross-functional teams to ensure high-quality outcomes for next-generation SoC and IP blocks.

Qualifications

• Minimum 15 years of ASIC physical design experience.
• Proven tape-out experience on advanced process nodes.
• Strong scripting in Tcl/Perl/Python to automate flows.
• Deep knowledge of DFM and STA constraints.
• Leadership and mentoring capabilities.

Responsibilities

• Own the physical implementation—from RTL to GDSII.
• Lead floorplanning, placement, routing, clock tree synthesis, and STA.
• Develop low-power strategies including gating and multi-voltage designs.
• Drive tooling and methodologies to boost efficiency.
• Collaborate with architecture and verification teams and mentor engineers.

Skills

ASIC physical design

Floor planning

Place & route

Clock tree synthesis

Static timing analysis

Scripting: Tcl/Perl/Python

Mentoring

Team leadership

Power/DFM

Education

Bachelor's or Master's in Electrical/Electronics

Tools

Cadence Innovus/Tempus

Synopsys Fusion Compiler/PrimeTime

Ansys RedHawk/PathFinder

Job description

Nalys is a highly dynamic engineering and technology consulting company dedicated to high-tech projects, providing specialized expertise to top industry players. We are currently recruiting on behalf of a major client in the semiconductor industry, focusing on the development of cutting-edge SoC (System on Chip) and IP blocks.

Le poste :

As a Principal Physical Design Engineer consulting for Nalys, you will act as a core technical leader responsible for steering and executing complex physical design activities for advanced SoC and IP blocks. You will take full ownership of the physical implementation from RTL to GDSII, handling critical tasks such as floor planning, power distribution, place and route, clock tree synthesis, and static timing analysis (STA). Your expertise will be crucial in meeting stringent power, performance, and area constraints for next-generation semiconductor products.
In this role, you will proactively optimize workflows, design methodologies, and automation scripts to boost overall engineering efficiency, reduce turnaround times, and elevate design quality. You will collaborate closely with cross-functional architecture and verification teams to troubleshoot complex technical roadblocks and guarantee robust, flawless implementations. Furthermore, you will define comprehensive low-power strategies—including clock gating, power gating, and multi-voltage designs—while actively evaluating next-generation EDA tools to enhance the team's capabilities. A key aspect of your role involves mentoring fellow engineers, sharing your deep technical knowledge, and fostering continuous growth within the physical design department.

Profil recherché :

We are seeking a highly accomplished engineering professional holding a Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a closely related technical field. You must bring a minimum of 15 years of experience in ASIC physical design, highlighted by a proven track record of successful tape-outs on advanced process nodes.
Deep, hands-on proficiency with industry-standard EDA tools (such as Cadence Innovus/Tempus, Synopsys Fusion Compiler/PrimeTime, or Ansys RedHawk/PathFinder) is mandatory. You must possess advanced programming skills in scripting languages like Tcl, Perl, or Python to drive complex flow automation. A comprehensive understanding of semiconductor physics, Design for Manufacturability (DFM) principles, and static timing analysis constraints is essential. You are recognized for your outstanding analytical problem-solving capabilities, your ability to lead ambitious technical initiatives, and your dedication to guiding and supporting team members in a fast-paced, collaborative environment.