Digital IC Design Engineer

Vivid Resourcing; Vlaams-Brabant; On-site; EUR 70,000 - 105,000; Full time

Job summary

Vivid Resourcing Ltd is seeking a Digital IC Design Engineer in Belgium to contribute to RTL development and advanced ASIC projects, from concept through verification. You will translate architectural specifications into high-quality RTL designs and collaborate across architecture, verification, physical design and validation teams to deliver robust silicon.

The role emphasizes Verilog/SystemVerilog proficiency, RTL simulation, debugging, and design reviews, with responsibility for performance,

Qualifications

• Master's degree in Electronics/Electrical Eng, CS or related.
• Experience in Digital IC Design with RTL emphasis.
• Strong proficiency in Verilog/SystemVerilog.
• Solid understanding of digital design, logic, and microarchitecture.
• Experience with RTL simulation, debugging and verification.
• Familiarity with ASIC design flows (synthesis and physical).
• Knowledge of timing constraints, clock domains and low-power design.
• Experience with industry-standard EDA tools.
• Strong analytical and problem-solving skills in a multidisciplinary team.

Responsibilities

• Develop, implement and maintain RTL designs using Verilog and SystemVerilog.
• Translate specifications into synthesizable RTL.
• Contribute to microarchitecture definition and design docs.
• Optimize RTL for performance, power and area.
• Collaborate with verification engineers for functional verification.
• Work with synthesis and physical design teams for implementation.
• Perform RTL simulation, debugging and design reviews.
• Support full ASIC development lifecycle from spec to silicon validation.
• Identify and resolve design issues ensuring quality and reliability.

Skills

RTL development

Verilog/SystemVerilog

Digital design principles

Timing/clock domains

Problem-solving

Education

Master's degree in Electronics Eng / Electrical Eng / CS

Tools

Industry-standard EDA tools

Job description

We are looking for a Digital IC Design Engineer with a strong focus on RTL development to join an innovative semiconductor engineering team working on the design and development of advanced integrated circuits.

In this role, you will be responsible for translating architectural specifications into high-quality RTL designs, contributing to the development of complex digital systems from initial concept through to implementation and verification. You will work closely with colleagues across architecture, verification, physical design and validation to ensure robust, efficient and high-performance silicon solutions.

This is an opportunity to work on challenging ASIC development projects, taking ownership of key design blocks while contributing to the development of next-generation semiconductor technologies.

Key Responsibilities

• Develop, implement and maintain RTL designs using Verilog and SystemVerilog.
• Translate architectural specifications and design requirements into synthesizable RTL.
• Contribute to microarchitecture definition and design documentation.
• Optimise RTL for performance, power consumption and area (PPA).
• Collaborate with verification engineers to support functional verification and debugging.
• Work closely with synthesis and physical design teams to ensure successful implementation.
• Perform RTL simulation, debugging and design reviews.
• Support the full ASIC development lifecycle, from specification through to silicon validation.
• Identify and resolve design issues, ensuring quality and reliability throughout development.

Requirements

• Master's degree in Electronics Engineering, Electrical Engineering, Computer Science or a related discipline.
• Experience in Digital IC Design, with a strong focus on RTL development.
• Strong proficiency in Verilog and/or SystemVerilog.
• Good understanding of digital design principles, logic design and microarchitecture.
• Experience with RTL simulation, debugging and functional verification methodologies.
• Familiarity with ASIC design flows, including synthesis and physical implementation.
• Knowledge of timing constraints, clock domains and low-power design techniques is advantageous.
• Experience with industry-standard EDA tools is beneficial.
• Strong analytical and problem-solving skills, with the ability to work effectively within a multidisciplinary engineering team.

The Offer

• A salary & benefits package commensurate with experience