Physical ASIC Design Implementation Engineer

IMEC; Belgique; On-site; EUR 90,000 - 135,000; Full time

Benefits offered by this job

Market-competitive salary

Fringe benefits

Imec Academy

Job summary

IMEC in Leuven is seeking an experienced Physical ASIC Design Engineer within the DSRD group to lead back-end layout tasks and sign-off activities for advanced node designs. You will interact directly with customers and drive the complete Cadence Innovus Place&Route flow.

You will contribute to hierarchical designs, power reduction strategies, and tight timing closure across multiple corners, working in an international team with strong emphasis on communication and collaboration.

Qualifications

• 8+ years in physical implementation for advanced nodes (12–5nm) and hierarchical designs.
• Experience with power-reduction techniques (gated clocks, voltage domains, memory retention, power domains).
• Strong debugging skills for tools/flows/designs.
• Excellent English communication and ability to work in an international team.
• Customer interaction experience.

Responsibilities

• Set up the Cadence Innovus Place&Route flow for the specific library set and foundry node used.
• Lead partitioning for hierarchical designs and manage top-level SDC timing budgets.
• Drive sign-off closure for tape-out in collaboration with Physical Design team.
• Interface with customers to discuss requirements.
• Support DSRD backend group with sign-off timing, power, and physical verification.

Skills

ASIC design

Cadence Innovus

Place & Route

Timing analysis

Power reduction

Debugging

Customer interaction

English communication

Tools

Cadence Innovus

Tempus

Voltus

DRC/LVS tools

Job description

Organisation/Company IMEC Research Field Technology » Nanotechnology Researcher Profile Other Profession Positions Master Positions Application Deadline 21 Nov 2026 - 23:59 (Europe/Brussels) Country Belgium Type of Contract Permanent Job Status Full-time Is the job funded through the EU Research Framework Programme? Not funded by a EU programme Is the Job related to staff position within a Research Infrastructure? No

Offer Description

As Physical ASIC design engineer within DSRD, you will be in direct contact with our customers for future projects. You will have full understanding of the complete Cadence Innovus Place&Route flow.

What you will do

For more than 25 years, imec has been offering an ASIC prototyping and production service to worldwide companies. Imec helps its customers to design their integrated circuits (chips) and bring them from the prototype to the production stage. Our list of customers includes more than 900 universities and companies worldwide. For the further extension of the physical digital implementation group (Back-End group) in DSRD, we are looking for a highly motivated engineer.

DSRD, as part of imec, has an extensive industrial experience, contacts with leading industrial foundries, and long-standing relationships with all the main EDA tool vendors and IP providers. This unit supports worldwide customers in the layout, prototype, fabrication and test of advanced electronic products.

As Physical ASIC design engineer within DSRD, you will be in direct contact with our customers for future projects. You will have full understanding of the complete Cadence Innovus Place&Route flow:

• Set up the flow for the specific library set and foundry node used
• Set up low power design (UPF)
• Floorplanning & power grid design
• Detailed Timing Driven Placement
• Clock Tree Synthesis
• Scan chain re-stitching
• Detailed Timing Driven Route (incl. SI)
• IPO’s (in-place optimization) to get the timing in all corners correct
• Solve setup & hold violations
• Sign-off extraction (SPEF/QUANTUS)
• Sign-off timing (TEMPUS)
• Sign-off Power analysis (VOLTUS)
• Physical verification (DRC, ERC, LVS, ANT)
• Logic equivalent check

For hierarchical designs you can take the lead for partitioning and split the top level SDC file into timing budget requirements/constraints of the sub-blocks. You will work directly with the Physical Design implementation team during the entire chip design cycle to drive signoff closure for tape-out, You are also the technical voice to the customer to discuss his specifications.

• You have at least 8 years of experience in physical implementation in advanced nodes (12 – 5nm) and hierarchical designs.
• You have experience in power reduction techniques like gated clocks, voltage domains, memory retention and switch off power domains.
• You have experience in debugging any tool/flow/design issue.
• You have excellent communication skills (English is a must) and can work within an international team.
• You like to interact with customers.

Languages ENGLISH Level Excellent

Research Field Technology

Additional Information

What we do for you

We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its office in Leuven. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will define the society of tomorrow.

We are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth.

We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits.